C8051F560-IQ Silicon Laboratories Inc, C8051F560-IQ Datasheet - Page 86

IC 8051 MCU 32K FLASH 32-QFP

C8051F560-IQ

Manufacturer Part Number
C8051F560-IQ
Description
IC 8051 MCU 32K FLASH 32-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F56xr
Datasheets

Specifications of C8051F560-IQ

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-QFP
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F560DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1693

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F560-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F560-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F55x/56x/57x
Table 10.1. CIP-51 Instruction Set Summary (Continued)
86
SETB C
SETB bit
CPL C
CPL bit
ANL C, bit
ANL C, /bit
ORL C, bit
ORL C, /bit
MOV C, bit
MOV bit, C
JC rel
JNC rel
JB bit, rel
JNB bit, rel
JBC bit, rel
Program Branching
ACALL addr11
LCALL addr16
RET
RETI
AJMP addr11
LJMP addr16
SJMP rel
JMP @A+DPTR
JZ rel
JNZ rel
CJNE A, direct, rel
CJNE A, #data, rel
CJNE Rn, #data, rel
CJNE @Ri, #data, rel
DJNZ Rn, rel
DJNZ direct, rel
NOP
Note: Certain instructions take a variable number of clock cycles to execute depending on instruction alignment and
the FLRT setting (SFR Definition 14.3).
Mnemonic
Set Carry
Set direct bit
Complement Carry
Complement direct bit
AND direct bit to Carry
AND complement of direct bit to Carry
OR direct bit to carry
OR complement of direct bit to Carry
Move direct bit to Carry
Move Carry to direct bit
Jump if Carry is set
Jump if Carry is not set
Jump if direct bit is set
Jump if direct bit is not set
Jump if direct bit is set and clear bit
Absolute subroutine call
Long subroutine call
Return from subroutine
Return from interrupt
Absolute jump
Long jump
Short jump (relative address)
Jump indirect relative to DPTR
Jump if A equals zero
Jump if A does not equal zero
Compare direct byte to A and jump if not equal
Compare immediate to A and jump if not equal
Compare immediate to Register and jump if not
equal
Compare immediate to indirect and jump if not
equal
Decrement Register and jump if not zero
Decrement direct byte and jump if not zero
No operation
Description
Rev. 1.1
1
2
1
2
2
2
2
2
2
2
2
2
3
3
3
2
3
1
1
2
3
2
1
2
2
3
3
3
3
2
3
1
Bytes
1
2
1
2
2
2
2
2
2
2
2/(4-6)
2/(4-6)*
3/(5-7)*
3/(5-7)*
3/(5-7)*
4-6*
5-7*
6-8*
6-8*
4-6*
5-7*
4-6*
3-5*
2/(4-6)*
2/(4-6)*
4/(6-8)*
3/(6-8)*
3/(5-7)*
4/(6-8)*
2/(4-6)*
3/(5-7)*
1
Cycles
Clock
*

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