C8051F560-IQ Silicon Laboratories Inc, C8051F560-IQ Datasheet - Page 180

IC 8051 MCU 32K FLASH 32-QFP

C8051F560-IQ

Manufacturer Part Number
C8051F560-IQ
Description
IC 8051 MCU 32K FLASH 32-QFP
Manufacturer
Silicon Laboratories Inc
Series
C8051F56xr
Datasheets

Specifications of C8051F560-IQ

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-QFP
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F560DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1693

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F560-IQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051F560-IQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051F55x/56x/57x
SFR Definition 19.10. P3MASK: Port 3 Mask Register
SFR Address = 0xAF; SFR Page = 0x00
SFR Definition 19.11. P3MAT: Port 3 Match Register
SFR Address = 0xAE; SFR Page = 0x00
180
Note: P3.0 is available on 40-pin and 32-pin packages. P3.1-P3.7 are available on 40-pin packages
Note: P3.0 is available on 40-pin and 32-pin packages. P3.1-P3.7 are available on 40-pin packages
Name
Reset
Name
Reset
7:0
7:0
Bit
Bit
Type
Type
Bit
Bit
P3MASK[7:0]
P3MAT[7:0]
Name
Name
7
0
7
1
Port 1 Mask Value.
Selects P3 pins to be compared to the corresponding bits in P3MAT.
0: P3.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P3.n pin logic value is compared to P3MAT.n.
Port 3 Match Value.
Match comparison value used on Port 3 for bits in P3MAT which are set to 1.
0: P3.n pin logic value is compared with logic LOW.
1: P3.n pin logic value is compared with logic HIGH.
6
0
6
1
5
0
5
1
Rev. 1.1
4
P3MASK[7:0]
0
4
1
P3MAT[7:0]
R/W
R/W
Function
Function
3
0
3
1
2
0
2
1
1
0
1
1
0
0
0
1

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