C8051F560-IQ Silicon Laboratories Inc, C8051F560-IQ Datasheet - Page 143

• Manufacturer Part Number: C8051F560-IQ
• Description: IC 8051 MCU 32K FLASH 32-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F56xr

Specifications of C8051F560-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-QFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F560DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1691 - KIT DEVELOPMENT FOR C8051F560
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1693

17.2. Configuring the External Memory Interface
Configuring the External Memory Interface consists of four steps:
1. Configure the Output Modes of the associated port pins as either push-pull or open-drain (push-pull is
2. Configure Port latches to “park” the EMIF pins in a dormant state (usually by setting them to logic 1).
3. Select the memory mode (on-chip only, split mode without bank select, split mode with bank select, or
4. Set up timing to interface with off-chip memory or peripherals.
Each of these four steps is explained in detail in the following sections. The Port selection and Mode bits
are located in the EMI0CF register shown in SFR Definition .
17.3. Port Configuration
The External Memory Interface appears on Ports 1, 2 and 3 when it is used for off-chip memory access.
These ports are multiplexed so that low-order address lines are shared with the data lines. When the EMIF
is used, the Crossbar should be configured to skip over the /RD control line (P1.6) and the /WR control line
(P1.7) using the P1SKIP register and also skip over the ALE control line (P1.5). For more information
about configuring the Crossbar, see Section “19.6. Special Function Registers for Accessing and Configur-
ing Port I/O” on page 181. The EMIF pinout is shown inTable 17.1 on page 144.
The External Memory Interface claims the associated Port pins for memory operations ONLY during the
execution of an off-chip MOVX instruction. Once the MOVX instruction has completed, control of the Port
pins reverts to the Port latches or to the Crossbar settings for those pins. See Section “19. Port Input/Out-
put” on page 167 for more information about the Crossbar and Port operation and configuration. The Port
latches should be explicitly configured to “park” the External Memory Interface pins in a dormant
state, most commonly by setting them to a logic 1 .
During the execution of the MOVX instruction, the External Memory Interface will explicitly disable the driv-
ers on all Port pins that are acting as Inputs (Data[7:0] during a READ operation, for example). The Output
mode of the Port pins (whether the pin is configured as Open-Drain or Push-Pull) is unaffected by the
External Memory Interface operation, and remains controlled by the PnMDOUT registers. In most cases,
the output modes of all EMIF pins should be configured for push-pull mode.
most common), and skip the associated pins in the crossbar.
off-chip only).
Rev. 1.1
C8051F55x/56x/57x
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