C8051F560-IQ Silicon Laboratories Inc, C8051F560-IQ Datasheet - Page 56

• Manufacturer Part Number: C8051F560-IQ
• Description: IC 8051 MCU 32K FLASH 32-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F56xr

Specifications of C8051F560-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-QFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F560DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1691 - KIT DEVELOPMENT FOR C8051F560
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1693

C8051F55x/56x/57x
Gain Register Definition 6.1. ADC0GNH: ADC0 Selectable Gain High Byte
Indirect Address = 0x04;
Gain Register Definition 6.2. ADC0GNL: ADC0 Selectable Gain Low Byte
Indirect Address = 0x07;
56
Note: This register is accessed indirectly; See
Note: This register is accessed indirectly; See
Name
Reset
Name
Reset
7:0
7:4
3:0
Bit
Bit
Type
Type
Bit
Bit
GAINH[7:0] ADC0 Gain High Byte.
GAINL[3:0] ADC0 Gain Lower 4 Bits.
Reserved
Name
Name
7
1
7
0
See Section 6.3.1 for details on calculating the value for this register.
See Figure 6.3.1 for details for setting this register.
This register is only accessed indirectly through the ADC0H and ADC0L register.
Must Write 0000b
6
1
6
0
GAINL[3:0]
W
5
1
5
0
Section 6.3.2
Section 6.3.2
Rev. 1.1
4
1
4
0
GAINH[7:0]
W
for details for writing this register.
for details for writing this register.
Function
Function
Reserved
W
3
1
3
0
Reserved
W
2
1
2
0
Reserved
W
1
0
1
0
Reserved
W
0
0
0
0