C8051F560-IQ Silicon Laboratories Inc, C8051F560-IQ Datasheet - Page 14

• Manufacturer Part Number: C8051F560-IQ
• Description: IC 8051 MCU 32K FLASH 32-QFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F56xr

Specifications of C8051F560-IQ

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 32-QFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 25
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 25x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2304 B
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 25
• Operating Supply Voltage: 1.8 V to 5.25 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F560DK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1691 - KIT DEVELOPMENT FOR C8051F560
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1693

C8051F55x/56x/57x
SFR Definition 16.2. RSTSRC: Reset Source ............................................................ 141
SFR Definition 17.1. EMI0CN: External Memory Interface Control ............................ 145
SFR Definition 17.2. EMI0CF: External Memory Configuration .................................. 146
SFR Definition 17.3. EMI0TC: External Memory Timing Control ................................ 150
SFR Definition 18.1. CLKSEL: Clock Select ............................................................... 156
SFR Definition 18.2. OSCICN: Internal Oscillator Control .......................................... 158
SFR Definition 18.3. OSCICRS: Internal Oscillator Coarse Calibration ...................... 159
SFR Definition 18.4. OSCIFIN: Internal Oscillator Fine Calibration ............................ 159
SFR Definition 18.5. CLKMUL: Clock Multiplier .......................................................... 161
SFR Definition 18.6. OSCXCN: External Oscillator Control ........................................ 163
SFR Definition 19.1. XBR0: Port I/O Crossbar Register 0 .......................................... 174
SFR Definition 19.2. XBR1: Port I/O Crossbar Register 1 .......................................... 175
SFR Definition 19.3. XBR2: Port I/O Crossbar Register 1 .......................................... 176
SFR Definition 19.4. P0MASK: Port 0 Mask Register ................................................. 177
SFR Definition 19.5. P0MAT: Port 0 Match Register .................................................. 177
SFR Definition 19.6. P1MASK: Port 1 Mask Register ................................................. 178
SFR Definition 19.7. P1MAT: Port 1 Match Register .................................................. 178
SFR Definition 19.8. P2MASK: Port 2 Mask Register ................................................. 179
SFR Definition 19.9. P2MAT: Port 2 Match Register .................................................. 179
SFR Definition 19.10. P3MASK: Port 3 Mask Register ............................................... 180
SFR Definition 19.11. P3MAT: Port 3 Match Register ................................................ 180
SFR Definition 19.12. P0: Port 0 ................................................................................. 181
SFR Definition 19.13. P0MDIN: Port 0 Input Mode ..................................................... 182
SFR Definition 19.14. P0MDOUT: Port 0 Output Mode .............................................. 182
SFR Definition 19.15. P0SKIP: Port 0 Skip ................................................................. 183
SFR Definition 19.16. P1: Port 1 ................................................................................. 183
SFR Definition 19.17. P1MDIN: Port 1 Input Mode ..................................................... 184
SFR Definition 19.18. P1MDOUT: Port 1 Output Mode .............................................. 184
SFR Definition 19.19. P1SKIP: Port 1 Skip ................................................................. 185
SFR Definition 19.20. P2: Port 2 ................................................................................. 185
SFR Definition 19.21. P2MDIN: Port 2 Input Mode ..................................................... 186
SFR Definition 19.22. P2MDOUT: Port 2 Output Mode .............................................. 186
SFR Definition 19.23. P2SKIP: Port 2 Skip ................................................................. 187
SFR Definition 19.24. P3: Port 3 ................................................................................. 187
SFR Definition 19.25. P3MDIN: Port 3 Input Mode ..................................................... 188
SFR Definition 19.26. P3MDOUT: Port 3 Output Mode .............................................. 188
SFR Definition 19.27. P3SKIP: Port 3Skip .................................................................. 189
SFR Definition 19.28. P4: Port 4 ................................................................................. 189
SFR Definition 19.29. P4MDOUT: Port 4 Output Mode .............................................. 190
SFR Definition 20.1. LIN0ADR: LIN0 Indirect Address Register ................................. 198
SFR Definition 20.2. LIN0DAT: LIN0 Indirect Data Register ....................................... 198
SFR Definition 20.3. LIN0CF: LIN0 Control Mode Register ........................................ 199
SFR Definition 21.1. CAN0CFG: CAN Clock Configuration ........................................ 215
SFR Definition 22.1. SMB0CF: SMBus Clock/Configuration ...................................... 222
SFR Definition 22.2. SMB0CN: SMBus Control .......................................................... 224
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