PIC18LF452-I/PT Microchip Technology, PIC18LF452-I/PT Datasheet - Page 137

• Manufacturer Part Number: PIC18LF452-I/PT
• Description: IC MCU FLASH 16KX16 A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF452-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: MSSP/SPI/I2C/PSP/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

REGISTER 15-3:
2002 Microchip Technology Inc.
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
bit 7
SMP: Slew Rate Control bit
In Master or Slave mode:
1 = Slew rate control disabled for Standard Speed mode (100 kHz and 1 MHz)
0 = Slew rate control enabled for High Speed mode (400 kHz)
CKE: SMBus Select bit
In Master or Slave mode:
1 = Enable SMBus specific inputs
0 = Disable SMBus specific inputs
D/A: Data/Address bit
In Master mode:
Reserved
In Slave mode:
1 = Indicates that the last byte received or transmitted was data
0 = Indicates that the last byte received or transmitted was address
P: STOP bit
1 = Indicates that a STOP bit has been detected last
0 = STOP bit was not detected last
Note:
S: START bit
1 = Indicates that a start bit has been detected last
0 = START bit was not detected last
Note:
R/W: Read/Write bit Information (I
In Slave mode:
1 = Read
0 = Write
1 = Transmit is in progress
0 = Transmit is not in progress
Note:
UA: Update Address (10-bit Slave mode only)
1 = Indicates that the user needs to update the address in the SSPADD register
0 = Address does not need to be updated
BF: Buffer Full Status bit
In Transmit mode:
1 = Receive complete, SSPBUF is full
0 = Receive not complete, SSPBUF is empty
In Receive mode:
1 = Data transmit in progress (does not include the ACK and STOP bits), SSPBUF is full
0 = Data transmit complete (does not include the ACK and STOP bits), SSPBUF is empty
Legend:
R = Readable bit
- n = Value at POR
In Master mode:
SSPSTAT: MSSP STATUS REGISTER (I
R/W-0
Note:
SMP
This bit is cleared on RESET and when SSPEN is cleared.
This bit is cleared on RESET and when SSPEN is cleared.
This bit holds the R/W bit information following the last address match. This bit is only
valid from the address match to the next START bit, STOP bit, or not ACK bit.
ORing this bit with SEN, RSEN, PEN, RCEN, or ACKEN will indicate if the MSSP is
in IDLE mode.
R/W-0
CKE
W = Writable bit
’1’ = Bit is set
D/A
R-0
2
C mode only)
R-0
P
2
C MODE)
U = Unimplemented bit, read as ‘0’
’0’ = Bit is cleared
R-0
S
R/W
R-0
PIC18FXX2
x = Bit is unknown
R-0
UA
DS39564B-page 135
R-0
BF
bit 0