PIC18LF452-I/PT Microchip Technology, PIC18LF452-I/PT Datasheet - Page 102

• Manufacturer Part Number: PIC18LF452-I/PT
• Description: IC MCU FLASH 16KX16 A/D 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18LF452-I/PT

• Program Memory Type: FLASH
• Program Memory Size: 32KB (16K x 16)
• Package / Case: 44-TQFP, 44-VQFP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 34
• Eeprom Size: 256 x 8
• Ram Size: 1.5K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC18LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1.5 KB
• Interface Type: MSSP/SPI/I2C/PSP/USART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 34
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 1 mm
• Length: 10 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 10 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18FXX2
9.6
The Parallel Slave Port is implemented on the 40-pin
devices only (PIC18F4X2).
PORTD operates as an 8-bit wide Parallel Slave Port,
or microprocessor port when control bit, PSPMODE
(TRISE<4>) is set. It is asynchronously readable and
writable by the external world through RD control input
pin, RE0/RD and WR control input pin, RE1/WR.
It can directly interface to an 8-bit microprocessor data
bus. The external microprocessor can read or write the
PORTD latch as an 8-bit latch. Setting bit PSPMODE
enables port pin RE0/RD to be the RD input, RE1/WR
to be the WR input and RE2/CS to be the CS (chip
select) input. For this functionality, the corresponding
data direction bits of the TRISE register (TRISE<2:0>)
must be configured as inputs (set). The A/D port config-
uration bits PCFG2:PCFG0 (ADCON1<2:0>) must be
set, which will configure pins RE2:RE0 as digital I/O.
A write to the PSP occurs when both the CS and WR
lines are first detected low. A read from the PSP occurs
when both the CS and RD lines are first detected low.
The PORTE I/O pins become control inputs for the
microprocessor port when bit PSPMODE (TRISE<4>)
is set. In this mode, the user must make sure that the
TRISE<2:0> bits are set (pins are configured as digital
inputs), and the ADCON1 is configured for digital I/O.
In this mode, the input buffers are TTL.
FIGURE 9-11:
DS39564B-page 100
PORTD<7:0>
PSPIF
Parallel Slave Port
OBF
CS
WR
RD
IBF
Q1
PARALLEL SLAVE PORT WRITE WAVEFORMS
Q2
Q3
Q4
Q1
Q2
FIGURE 9-10:
One bit of PORTD
Note: I/O pin has protection diodes to V
Data Bus
Q3
Set Interrupt Flag
PSPIF (PIR1<7>)
WR LATD
or
PORTD
RD PORTD
RD LATD
Q4
TRIS Latch
Data Latch
Q
D
CK
Q1
EN
EN
Q
D
PORTD AND PORTE
BLOCK DIAGRAM
(PARALLEL SLAVE
PORT)
2002 Microchip Technology Inc.
Q2
Chip Select
Read
Write
Q3
TTL
DD
TTL
TTL
TTL
and V
Q4
SS
RDx
Pin
RD
CS
WR
.