IDT72V36102 IDT [Integrated Device Technology], IDT72V36102 Datasheet
IDT72V36102
Available stocks
Related parts for IDT72V36102
IDT72V36102 Summary of contents
Page 1
... Memory storage capacity: IDT72V3682 – 16,384 IDT72V3692 – 32,768 IDT72V36102 – 65,536 • • • • • Supports clock frequencies up to 100MHz • • • • • Fast access times of 6.5ns • ...
Page 2
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 DESCRIPTION The IDT72V3682/72V3692/72V36102 are designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are mono- lithic, ...
Page 3
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 whether or not the FIFO memory is empty. FF shows whether the memory is full or not. The IR and ...
Page 4
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 PIN DESCRIPTIONS Symbol Name I/O A0-A35 Port A Data I/0 AEA Port A Almost- O Empty Flag (Port A) less ...
Page 5
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 PIN DESCRIPTIONS (CONTINUED) Symbol Name I/O MBA Port A Mailbox I Select MBB Port B Mailbox I Select MBF1 Mail1 ...
Page 6
... MHZ O ) vs. Clock Frequency ( COMMERCIAL TEMPERATURE RANGE Commercial –0.5 to +4.6 –0 +0.5 CC –0 +0.5 CC ±20 ±50 ±50 ±400 –65 to 150 IDT72V3682 IDT72V3692 IDT72V36102 Commercial CLK Min. Typ. = –4 mA 2.4 — — — — — — — ...
Page 7
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 DETERMINING ACTIVE CURRENT CONSUMPTION AND POWER DISSIPATION The I current for the graph in Figure 1 was taken while simultaneously ...
Page 8
... IDT72V3682L15 IDT72V3692L15 IDT72V36102L15 Min. Max. Unit — 66.7 MHz 15 — — — — ns 4.5 — ns 4.5 — — ns 7.5 — — — ...
Page 9
... Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH. TM IDT72V3682L10 IDT72V3692L10 IDT72V36102L10 Min (1) and COMMERCIAL TEMPERATURE RANGE = IDT72V3682L15 IDT72V3692L15 IDT72V36102L15 Max. Min. Max ...
Page 10
... After this reset is complete, the first four writes to FIFO1 do not store data in the FIFO memory but load the offset registers in the order Y1, X1, Y2, X2. The port A data inputs used by the offset registers are (A10-A0), (A11-A0), or (A12- A0) for the IDT72V3682, IDT72V3692, or IDT72V36102, respectively. The RST2 X1 AND Y1 REGlSTERS ...
Page 11
... Valid programming values for the registers ranges from 1 to 16,380 for the IDT72V3682 32,764 for the IDT72V3692; and 1 to 65,532 for the IDT72V36102. After all the offset registers are programmed from port A, the port B Full/Input Ready flag (FFB/IRB) is set HIGH, and both FIFOs begin normal operation ...
Page 12
... Empty Flag HIGH; only then can data be read. (1,2) (3) (3) IDT72V36102 (X1+1) to [65,536-(Y1+1)] (65,536-Y1) to 65,535 32,768 65,536 (1,2) (3) (3) IDT72V36102 (X2+1) to [65,536-(Y2+1)] (65,536-Y2) to 65,535 32,768 65,536 12 COMMERCIAL TEMPERATURE RANGE Synchronized Synchronized to CLKB to CLKA EFB/ORB AEB ...
Page 13
... FIFO is less than or equal to [16,384-(Y+1)], [32,768-(Y+1)], or [65,536-(Y+1)] for the IDT72V3682, IDT72V3692, or IDT72V36102 respectively. Note that a data word present in the FIFO output register has been read from memory. Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock are required after a FIFO read for its Almost-Full flag to reflect the new level of fill ...
Page 14
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKA CLKB t RSTS RST1 FWFT FS1,FS0 FFA/IRA EFB/ORB t PRF AEB t PRF AFA t PRF MBF1 NOTES: 1. ...
Page 15
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLK t CLKH t CLKL CLKA FFA/IRA HIGH t ENS1 CSA t ENS1 W/RA t ENS2 MBA t ENS2 ...
Page 16
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLK t CLKH CLKB EFB/ORB HIGH CSB W/RB MBB ENB t EN B0-B35 (IDT Standard Mode ...
Page 17
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKA CSA LOW HIGH WRA t t ENS2 ENH MBA t ENS2 t ENH ENA HIGH IRA ...
Page 18
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKA CSA LOW WRA HIGH t t ENS2 MBA t t ENS2 ENA FFA HIGH t DS A0-A35 W1 t ...
Page 19
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKB CSB LOW W/RB LOW t t ENS2 ENH MBB t t ENH ENS2 ENB IRB HIGH ...
Page 20
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKB CSB LOW W/RB LOW t t ENS2 MBB t t ENS2 ENB FFB HIGH B0-B35 ...
Page 21
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB HIGH ORB B0 -B35 ...
Page 22
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLK t t CLKH CLKL CLKB CSB LOW W/RB HIGH LOW MBB t ENS2 ENB EFB HIGH B0-B35 Previous ...
Page 23
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLK t t CLKH CLKL CLKA CSA LOW W/RA LOW LOW MBA t ENS2 ENA HIGH ORA A0 -A35 ...
Page 24
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLK t t CLKH CLKL CLKA CSA LOW LOW W/RA LOW MBA t ENS2 ENA EFA HIGH A0-A35 Previous ...
Page 25
... FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO Maximum FIFO Depth = 16,384 for the IDT72V3682, 32,768 for the IDT72V3692, 65,536 for the IDT72V36102. ...
Page 26
... FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO Maximum FIFO Depth = 16,384 for the IDT72V3682, 32,768 for the IDT72V3692, 65,536 for the IDT72V36102. ...
Page 27
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 CLKB t ENS1 CSB t ENS1 W/RB t ENS2 MBB t ENS2 ENB B0 - B35 CLKA MBF2 CSA W/RA ...
Page 28
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO 16,384 32,768 and 65,536 Timing Input t S Data, 1.5V Enable Input VOLTAGE WAVEFORMS SETUP AND HOLD TIMES Output Enable 1.5V t PLZ Low-Level ...
Page 29
ORDERING INFORMATION IDT XXXXXX X XX Device Type Power Speed NOTE: 1. Industrial temperature range is available by special order. DATASHEET DOCUMENT HISTORY 10/30/2000 pgs and 29. 03/27/2001 pgs. 6 and 7. 11/04/2003 ...