IDT72V36102 IDT [Integrated Device Technology], IDT72V36102 Datasheet - Page 17

• Manufacturer Part Number: IDT72V36102
• Description: 3.3 VOLT CMOS SyncBiFIFO-TM
• Manufacturer: IDT [Integrated Device Technology]

NOTE:
1. t
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
A0 - A35
B0 -B35
If the time between the rising CLKA edge and rising CLKB edge is less than t
cycle later than shown.
SKEW1
CLKA
CLKB
W/RB
WRA
MBA
ORB
MBB
CSA
ENA
CSB
ENB
IRA
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
HIGH
FIFO1Empty
HIGH
LOW
LOW
LOW
HIGH
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
t
t
ENS2
t
ENS2
DS
W1
t
Old Data in FIFO1 Output Register
SKEW1
t
t
t
ENH
DH
ENH
(1)
t
CLKH
1
t
CLK
t
CLKL
SKEW1
TM
, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
17
2
t
CLKH
t
CLK
t
CLKL
t
POR
3
t
A
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
POR
t
ENH
W1
4679 drw 11