IDT72V36102 IDT [Integrated Device Technology], IDT72V36102 Datasheet - Page 19

• Manufacturer Part Number: IDT72V36102
• Description: 3.3 VOLT CMOS SyncBiFIFO-TM
• Manufacturer: IDT [Integrated Device Technology]

NOTE:
1. t
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
B0 - B35
A0 -A35
If the time between the rising CLKB edge and rising CLKA edge is less than t
cycle later than shown.
SKEW1
CLKA
W/RA
CLKB
W/RB
MBB
ORA
MBA
CSB
CSA
ENB
ENA
IRB
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
FIFO2 Empty
LOW
LOW
HIGH
LOW
LOW
LOW
Figure 10. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)
t
t
ENS2
ENS2
t
DS
W1
Old Data in FIFO2 Output Register
t
SKEW1
t
t
ENH
t
DH
ENH
(1)
t
CLKH
1
t
CLK
t
CLKL
SKEW1
TM
t
, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
CLKH
19
2
t
CLK
t
POR
t
3
A
t
CLKL
t
ENS2
COMMERCIAL TEMPERATURE RANGE
t
POR
t
ENH
W1
4679 drw 13