IDT72V36102 IDT [Integrated Device Technology], IDT72V36102 Datasheet - Page 23

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IDT72V36102

Manufacturer Part Number
IDT72V36102
Description
3.3 VOLT CMOS SyncBiFIFO-TM
Manufacturer
IDT [Integrated Device Technology]
Datasheet

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NOTE:
1. t
IDT72V3682/72V3692/72V36102 3.3V CMOS SyncBiFIFO
16,384 x 36 x 2, 32,768 x 36 x 2 and 65,536 x 36 x 2
B0 - B35
A0 -A35
CLKB edge is less than t
SKEW1
CLKB
CLKA
W/RA
W/RB
ORA
CSA
MBA
ENA
CSB
MBB
ENB
IRB
is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
LOW
FIFO2 FULL
LOW
LOW
LOW
HIGH
LOW
Previous Word in FIFO2 Output Register
t
CLKH
SKEW1
t
CLK
, then IRB may transition HIGH one CLKB cycle later than shown.
t
Figure 14. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
ENS2
t
CLKL
t
SKEW1
t
t
ENH
A
(1)
1
t
CLKH
TM
t
CLK
23
t
CLKL
2
Next Word From FIFO2
t
PIR
t
t
ENS2
ENS2
t
DS
COMMERCIAL TEMPERATURE RANGE
To FIFO2
Write
t
t
t
PIR
t
ENH
DH
ENH
4679 drw 17

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