IDT71321 Integrated Device Technology, IDT71321 Datasheet

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IDT71321

Manufacturer Part Number
IDT71321
Description
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
Manufacturer
Integrated Device Technology
Datasheet

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FEATURES:
• High-speed access
• Low-power operation
• Two
• MASTER IDT71321 easily expands data bus width to 16-
• On-chip port arbitration logic (IDT71321 only)
• Fully asynchronous operation from either port
• Battery backup operation —2V data retention (LA Only)
• TTL-compatible, single 5V 10% power supply
• Available in popular hermetic and plastic packages
• Industrial temperature range (–40 C to +85 C) is avail-
FUNCTIONAL BLOCK DIAGRAM
COMMERCIAL TEMPERATURE RANGE
©1996 Integrated Device Technology, Inc.
NOTES:
1. IDT71321 (MASTER):
2. Open drain output: requires pullup
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
—Commercial: 20/25/35/45/55ns (max.)
—IDT71321/IDT71421SA
—Active: 550mW (typ.)
—Standby: 5mW (typ.)
—IDT71321/421LA
—Active: 550mW (typ.)
—Standby: 1mW (typ.)
or-more-bits using SLAVE IDT71421
BUSY
Integrated Device Technology, Inc.
able, tested to military electrical specifications
is open drain output and
requires pullup resistor of 270 .
IDT71421 (SLAVE):
resistor of 270 .
INT
output flag on IDT71321;
flags for port-to-port communications
BUSY
BUSY
I/O
is input.
BUSY
0L
- I/O
R/
INT
L
(1,2)
A
OE
CE
A
For latest information contact IDT’s web site at www.idt.com or fax-on-demand at 408-492-8391.
W
10L
0L
7L
L
(2)
L
L
L
BUSY
HIGH-SPEED 2K x 8
DUAL-PORT STATIC RAM
WITH INTERRUPTS
input on IDT71421
Address
Decoder
R/
OE
CE
W
L
L
L
11
Control
I/O
6.03
DESCRIPTION:
Port Static RAMs with internal interrupt logic for interproces-
sor communications. The IDT71321 is designed to be used
as a stand-alone 8-bit Dual-Port RAM or as a "MASTER"
Dual-Port RAM together with the IDT71421 "SLAVE" Dual-
Port in 16-bit-or-more word width systems. Using the IDT
MASTER/SLAVE Dual-Port RAM approach in 16-or-more-
bit memory system applications results in full speed, error-
free operation without the need for additional discrete logic.
rate control, address, and I/O pins that permit independent,
asynchronous access for reads or writes to any location in
memory. An automatic power down feature, controlled by
CE
low standby power mode.
ogy, these devices typically operate on only 550mW of
power. Low-power (LA) versions offer battery backup data
retention capability, with each Dual-Port typically consum-
ing 200 W from a 2V battery.
pin PLCC, a 64-pin TQFP, and a 64-pin STQFP.
ARBITRATION
INTERRUPT
MEMORY
Both devices provide two independent ports with sepa-
Fabricated using IDT's CMOS high-performance technol-
The IDT71321/IDT71421 devices are packaged in a 52-
ARRAY
, permits the on chip circuitry of each port to enter a very
LOGIC
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-
and
Control
I/O
11
Decoder
Address
OE
R/
CE
W
R
R
R
IDT71321SA/LA
IDT71421SA/LA
2691 drw 01
R/
OE
CE
BUSY
OCTOBER 1996
I/O
INT
A
A
W
R
R
10R
0R
R
0R
R
(2)
-I/O
R
(1,2)
7R
DSC-2691/6
1

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IDT71321 Summary of contents

Page 1

... Two flags for port-to-port communications INT • MASTER IDT71321 easily expands data bus width to 16- or-more-bits using SLAVE IDT71421 • On-chip port arbitration logic (IDT71321 only) • output flag on IDT71321; BUSY BUSY • ...

Page 2

... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS PIN CONFIGURATIONS (1,2) NDEX IDT71321/421 J52 PLCC TOP VIEW ( ...

Page 3

... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS DC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Test Conditions I Dynamic Operating and Current (Both Ports Outputs open, Active MAX I Standby Current and CE SB1 L (Both Ports - TTL ...

Page 4

... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS DATA RETENTION CHARACTERISTICS Symbol Parameter V V for Data Retention Data Retention Current CCDR (3) t Chip Deselect to Data CDR Retention Time (3) t Operation Recovery R Time NOTES 2V +25 C, and is not production tested. ...

Page 5

... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Read Cycle t Read Cycle Time RC t Address Access Time AA t Chip Enable Access Time ACE t Output Enable Access Time ...

Page 6

... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS TIMING WAVEFORM OF READ CYCLE NO. 2, EITHER SIDE CE OE DATA OUT I CC CURRENT I SS NOTES: 1. Timing depends on which signal is asserted last, 2. Timing depends on which signal is deaserted first and the address is valid prior to or coincidental with IH 4 ...

Page 7

... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS TIMING WAVEFORM OF WRITE CYCLE NO. 1, (R/ ADDRESS DATA (4) OUT DATA IN TIMING WAVEFORM OF WRITE CYCLE NO ADDRESS CE ( DATA IN NOTES must be High during all address transitions. ...

Page 8

... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Busy Timing (For Master lDT71321 Only) BUSY t Access Time from Address BAA BUSY t Disable Time from Address BDA BUSY ...

Page 9

... R NOTES: BUSY 1. t must be met for both Input (IDT71421, slave) or Output (IDT71321, master). WH BUSY 2. is asserted on port 'B' blocking R/ 3. All timing is the same for the left and right ports. Port 'A' may be either the left or right port. Port 'B' is opposite from port 'A'. ...

Page 10

... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS AC ELECTRICAL CHARACTERISTICS OVER THE OPERATING TEMPERATURE AND SUPPLY VOLTAGE RANGE Symbol Parameter Interrupt Timing t Address Set-up Time AS t Write Recovery Time WR t Interrupt Set Time INS t Interrupt Reset Time INR NOTE: 1. " ...

Page 11

... L L (2) MATCH NOTES: BUSY BUSY 1. Pins and are both outputs for IDT71321 (master). Both are L R BUSY inputs for IDT71421 (slave). outputs on the IDT71321 are open X drain, not push-pull outputs. On slaves the writes. 2. 'L' if the inputs to the opposite port were stable prior to the address and enable inputs of this port ...

Page 12

... L inhibit signal. Thus on the IDT71321/IDT71421 RAMs the Busy pin is an output if the part is Master (IDT71321), and the Busy pin is an input if the part is a Slave (IDT71421) as shown in Figure " ...

Page 13

... IDT71321SA/LA AND IDT71421SA/LA HIGH-SPEED DUAL-PORT STATIC RAM WITH INTERRUPTS ORDERING INFORMATION IDT XXXX A 999 Device Type Power Speed A A Package Process/ Temperature Range Blank 71321 71421 6.03 COMMERCIAL TEMPERATURE RANGE Commercial ( +70 C) 52-pin PLCC (J52-1) ...

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