IDT71321 Integrated Device Technology, IDT71321 Datasheet - Page 12

• Manufacturer Part Number: IDT71321
• Description: HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
• Manufacturer: Integrated Device Technology

IDT71321SA/LA AND IDT71421SA/LA
HIGH-SPEED 2K x 8 DUAL-PORT STATIC RAM WITH INTERRUPTS
FUNCTIONAL DESCRIPTION
The IDT71321/IDT71421 provides two ports with separate
control, address and I/O pins that permit independent access
for reads or writes to any location in memory. The IDT71321/
IDT71421 has an automatic power down feature controlled
by
permits the respective port to go into a standby mode when
not selected (
entire memory array is permitted.
INTERRUPTS
If the user chooses to use the interrupt function, a memory
location (mail box or message center) is assigned to each
port. The left port interrupt flag (
right port writes to memory location 7FE (HEX), where a write
is defined as the
port clears the interrupt by access address location 7FE
access when
Likewise, the right port interrupt flag (
the left port writes to memory location 7FF (HEX) and to clear
the interrupt flag (
memory location 7FF. The message (8 bits) at 7FE or 7FF
is user-defined, since it is an addressable SRAM location. If
the interrupt function is not used, address locations 7FE and
7FF are not used as mail boxes, but as part of the random
access memory. Refer to Table I for the interrupt opera-
tion.
BUSY LOGIC
Busy Logic provides a hardware indication that both ports of
the RAM have accessed the same location at the same time.
It also allows one of the two accesses to proceed and signals
the other side that the RAM is “Busy”. The Busy pin can then
be used to stall the access until the operation on the other
side is completed. If a write operation has been attempted
from the side that receives a busy indication, the write signal
is gated internally to prevent the write from proceeding.
The use of busy logic is not required or desirable for all
applications. In some cases it may be useful to logically OR
the busy outputs together and use any busy indication as an
interrupt source to flag the event of an illegal or illogical
operation. In slave mode the
a write inhibit input pin. Normal operation can be pro-
grammed by tying the
write operations can be prevented to a port by tying the Busy
pin for that port Low.
CE
. The
CE
CE
CE
controls on-chip power down circuitry that
CE
= V
R
INT
IH
= R/
=
). When a port is enabled, access to the
BUSY
OE
R
W
), the right port must access the
R =
= V
pins High. If desired, unintended
IL
V
BUSY
per the Truth Table. The left
IL,
INT
R/
L
W
INT
) is asserted when the
pin operates solely as
R
is a "Don't Care".
) is asserted when
6.03
The Busy outputs on the IDT71321 RAM (Master) are open
drain type outputs and require open drain resistors to operate.
If these RAMs are being expanded in depth, then the Busy
indication for the resulting array does not require the use of an
external AND gate.
WIDTH EXPANSION WITH BUSY LOGIC
MASTER/SLAVE ARRAYS
When expanding an RAM array in width while using busy
logic, one master part is used to decide which side of the RAM
array will receive a busy indication, and to output that indica-
tion. Any number of slaves to be addressed in the same
address range as the master, use the busy signal as a write
inhibit signal. Thus on the IDT71321/IDT71421 RAMs the
Busy pin is an output if the part is Master (IDT71321), and the
Busy pin is an input if the part is a Slave (IDT71421) as shown
in Figure 4.
If two or more master parts were used when expanding in
width, a split decision could result with one master indicating
busy on one side of the array and another master indicating
busy on one other side of the array. This would inhibit the write
operations from one port for part of a word and inhibit the write
operations from the other port for the other part of the word.
The Busy arbitration, on a Master, is based on the chip enable
and address signals only. It ignores whether an access is a
read or write. In a master/slave array, both address and chip
enable must be valid long enough for a busy flag to be output
from the master before the actual write pulse can be initiated
with either the R/
observe this timing can result in a glitched internal write inhibit
signal and corrupted data in the slave.
270
BUSY
Figure 4. Busy and chip enable routing for both width and depth
expansion with IDT71321 (Master) and (Slave) IDT71421 RAMs.
5 V
L
MASTER
Dual Port
RAM
BUSY
MASTER
Dual Port
RAM
BUSY
L
L
W
BUSY
BUSY
signal or the byte enables. Failure to
CE
CE
R
R
COMMERCIAL TEMPERATURE RANGE
SLAVE
Dual Port
RAM
BUSY
SLAVE
Dual Port
RAM
BUSY
L
L
BUSY
BUSY
CE
CE
R
R
2691 drw 16
BUSY
5 V
R
12
270