EVAL-ADT7467EBZ ON Semiconductor, EVAL-ADT7467EBZ Datasheet - Page 24

• Manufacturer Part Number: EVAL-ADT7467EBZ
• Description: BOARD EVALUATION FOR ADT7467
• Manufacturer: ON Semiconductor
• Series: dBCool®r

Specifications of EVAL-ADT7467EBZ

• Sensor Type: Temperature
• Sensing Range: -40°C ~ 120°C
• Interface: SMBus (2-Wire/I²C)
• Sensitivity: ±1.5°C
• Voltage - Supply: 3 V ~ 5.5 V
• Embedded: No
• Utilized Ic / Part: ADT7467
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADT7467
THERM Timer
The ADT7467 has an internal timer to measure THERM
assertion time. For example, the THERM input can be
connected to the PROCHOT output of a Pentium 4 CPU to
measure system performance. The THERM input can also be
connected to the output of a trip point temperature sensor.
The timer is started on the assertion of the THERM input and
stopped when THERM is deasserted. The timer counts THERM
times cumulatively, that is, the timer resumes counting on the
next THERM assertion. The THERM timer continues to
accumulate THERM assertion times until the timer is read (it is
cleared upon a read) or until it reaches full scale. If the counter
reaches full scale, it stops at that reading until cleared.
The 8-bit THERM timer register (0x79) is designed such that
Bit 0 is set to 1 upon the first THERM assertion. Once the
cumulative THERM assertion time exceeds 45.52 ms, Bit 1 of
the THERM timer is set and Bit 0 becomes the LSB of the timer
with a resolution of 22.76 ms (see Figure 31).
T
THERM
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100% BECAUSE
TEMPERATURE IS BELOW T
MIN
Figure 30. Asserting THERM Low as an Input
in Automatic Fan Speed Control Mode
MIN
THERM ASSERTED TO LOW AS AN INPUT:
FANS DO NOT GO TO 100% BECAUSE
TEMPERATURE IS ABOVE T
ARE ALREADY RUNNING
MIN
Rev. 3 | Page 24 of 77 | www.onsemi.com
AND FANS
It is important to be aware of the following when using the
THERM timer.
After a THERM timer is read (Register 0x79), the following
occurs:
•
•
If the THERM timer is read during a THERM assertion, the
following occurs:
•
•
•
•
The contents of the timer are cleared upon a read.
The F4P bit (Bit 5) of Interrupt Status Register 2 must be
cleared, assuming that the THERM timer limit has been
exceeded.
The contents of the timer are cleared.
Bit 0 of the THERM timer is set to 1 because a THERM
assertion is occurring.
The THERM timer increments from 0.
If the THERM timer limit (Register 0x7A) is 0x00, the F4P
bit is set.
(REG. 0x79)
(REG. 0x79)
(REG. 0x79)
THERM
THERM
THERM
THERM
THERM
THERM
TIMER
TIMER
TIMER
ACCUMULATE THERM LOW
ACCUMULATE THERM LOW
Figure 31.Understanding the THERM Timer
ASSERTION TIMES
ASSERTION TIMES
0 0 0
7 6 5
0 0 0
7 6 5
0 0 0
7 6 5
0
4
0
4
0
4
0 0 0 1
3 2 1 0
0 0 1 0
3 2 1 0
0 1 0 1
3 2 1 0
THERM ASSERTED ≥ 113.8ms
(91.04ms + 22.76ms)
THERM ASSERTED
THERM ASSERTED
≤ 22.76ms
≥ 45.52ms