EVAL-ADT7467EBZ ON Semiconductor, EVAL-ADT7467EBZ Datasheet - Page 22

• Manufacturer Part Number: EVAL-ADT7467EBZ
• Description: BOARD EVALUATION FOR ADT7467
• Manufacturer: ON Semiconductor
• Series: dBCool®r

Specifications of EVAL-ADT7467EBZ

• Sensor Type: Temperature
• Sensing Range: -40°C ~ 120°C
• Interface: SMBus (2-Wire/I²C)
• Sensitivity: ±1.5°C
• Voltage - Supply: 3 V ~ 5.5 V
• Embedded: No
• Utilized Ic / Part: ADT7467
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADT7467
Fan TACH measurements are made in parallel and are not
synchronized with the analog measurements in any way.
STATUS REGISTERS
The results of limit comparisons are stored in Interrupt Status
Register 1 and Interrupt Status Register 2. The status register bit
for each channel reflects the status of the last measurement and
limit comparison on that channel. If a measurement is within
limits, the corresponding status register bit is cleared to 0. If the
measurement is out of limit, the corresponding status register
bit is set to 1.
The state of the various measurement channels can be polled by
reading the status registers over the serial bus. In Bit 7 (OOL) of
Interrupt Status Register 1 (0x41), 1 means that an out-of-limit
event has been flagged in Interrupt Status Register 2. This
means that the user also should read Interrupt Status Register 2.
Alternatively, Pin 5 or Pin 9 can be configured as an SMBALERT
output. This hardware interrupt automatically notifies the
system supervisor of an out-of-limit condition. Reading the
status registers clears the appropriate status bit if the error
condition that caused the interrupt is absent. Status register bits
are sticky. Whenever a status bit is set, indicating an out-of-limit
condition, it remains set until read, even if the event that caused
it is absent. The only way to clear the status bit is to read the
status register after the event is absent. Interrupt mask registers
(0x74 and 0x75) allow masking of individual interrupt sources
to prevent an SMBALERT. However, if a masked interrupt
source goes out of limit, its associated status bit is set in the
interrupt status registers.
Status Register 1 (0x41)
Bit 7 (OOL) = 1 denotes that a bit in Status Register 2 is set and
that Status Register 2 should be read.
Bit 6 (R2T) = 1 indicates that Remote 2 temperature high or low
limit has been exceeded.
Bit 5 (LT) = 1 indicates that local temperature high or low limit
has been exceeded.
Bit 4 (R1T) = 1 indicates that Remote 1 temperature high or low
limit has been exceeded.
Bit 2 (V
exceeded.
Bit 1 (V
exceeded.
Status Register 2 (0x42)
Bit 7 (D2) = 1 indicates an open or short on D2+/D2– inputs.
Bit 6 (D1) = 1 indicates an open or short on D1+/D1– inputs.
CC
CCP
) = 1 indicates that V
) = 1 indicates that V
CC
CCP
high or low limit has been
high or low limit has been
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Bit 5 (F4P) = 1 indicates Fan 4 has dropped below minimum
speed. Alternatively, if the THERM function is used, it indicates
that the THERM limit has been exceeded.
Bit 4 (FAN3) = 1 indicates Fan 3 has dropped below minimum
speed.
Bit 3 (FAN2) = 1 indicates Fan 2 has dropped below minimum
speed.
Bit 2 (FAN1) = 1 indicates Fan 1 has dropped below minimum
speed.
Bit 1 (OVT) = 1 indicates a THERM overtemperature limit has
been exceeded.
INTERRUPTS
SMBALERT Interrupt Behavior
The ADT7467 can be polled for status, or an SMBALERT
interrupt can be generated for out-of-limit conditions. It is
important to note how the SMBALERT output and status bits
behave when writing interrupt handler software.
Figure 28 shows how the SMBALERT output and sticky status
bits behave. Once a limit is exceeded, the corresponding status
bit is set to 1. The status bit remains set until the error condition
subsides and the status register is read. The status bits are re-
ferred to as sticky because they remain set until read by software.
This ensures that an out-of-limit event cannot be missed if
software is polling the device periodically. Note that the
SMBALERT output remains low both for the duration that a
reading is out of limit and until the status register has been read.
This has implications on how software handles the interrupt.
Handling SMBALERT Interrupts
To prevent the system from being tied up with servicing inter-
rupts, it is recommend to handle the SMBALERT interrupt as
follows:
1.
2.
3.
HIGH LIMIT
TEMPERATURE
STATUS BIT
SMBALERT
“STICKY”
Detect the SMBALERT assertion.
Enter the interrupt handler.
Read the status registers to identify the interrupt source.
Figure 28. SMBALERT and Status Bit Behavior
TEMP BACK IN LIMIT
(STATUS BIT STAYS SET)
(TEMP BELOW LIMIT)
CLEARED ON READ