MC56F8323EVM Freescale Semiconductor, MC56F8323EVM Datasheet - Page 29

• Manufacturer Part Number: MC56F8323EVM
• Description: KIT EVALUATION FOR MC56F8323
• Manufacturer: Freescale Semiconductor
• Type: DSPr

Specifications of MC56F8323EVM

• Contents: Module and Misc Hardware
• Processor To Be Evaluated: MC56F8322 and MC56F8323
• Data Bus Width: 16 bit
• Interface Type: RS-232
• For Use With/related Products: MC56F8322, MC56F8323
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Freescale Semiconductor
Preliminary
Signal Name
(GPIOC6)
(GPIOC5)
(GPIOC4)
(RXD0)
RESET
(TXD0)
IRQA
(V
TC0
TC1
TC3
PP
)
Table 2-2 Signal and Package Information for the 64-Pin LQFP
Pin No.
64
63
12
1
2
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Schmitt
Output
Output
Output
Output
Output
Output
Input/
Input/
Input/
Input/
Input/
Input/
Type
Input
Input
Input
Input
Input
State During
enabled
enabled
enabled
enabled
enabled
pull-up
pull-up
pull-up
pull-up
pull-up
Reset
56F8323 Technical Data, Rev. 17
Input,
Input,
Input,
Input,
Input,
TC0 — Timer C, Channel 0
Transmit Data — SCI0 transmit data output
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TC0.
TC1 — Timer C, Channel 1
Receive Data — SCI0 receive data input
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TC1.
TC3 — Timer C Channel 3
Port C GPIO — This GPIO pin can be individually programmed as
an input or output pin.
After reset, the default state is TC3.
External Interrupt Request A — The IRQA input is an
asynchronous external interrupt request during Stop and Wait mode
operation. During other operating modes, it is a synchronized
external interrupt request which indicates an external device is
requesting service. It can be programmed to be level-sensitive or
negative-edge-triggered
V
Reset — This input is a direct hardware reset on the processor.
When RESET is asserted low, the device is initialized and placed in
the reset state. A Schmitt trigger input is used for noise immunity.
The internal reset signal will be deasserted synchronous with the
internal clocks after a fixed number of internal clocks.
To ensure complete hardware reset, RESET and TRST should be
asserted together. The only exception occurs in a debugging
environment when a hardware device reset is required and the
JTAG/EOnCE module must not be reset. In this case, assert RESET,
but do not assert TRST.
PP
— This pin is used for Flash debugging purposes.
Signal Description
Signal Pins
29