EVAL-ADUC847QS Analog Devices Inc, EVAL-ADUC847QS Datasheet - Page 99

• Manufacturer Part Number: EVAL-ADUC847QS
• Description: KIT DEV FOR ADUC847 QUICK START
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC847QS

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 68. SPI MASTER MODE TIMING (CPHA = 1) Parameter
t
t
t
t
t
t
t
t
t
____________________________________________
1
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
Characterized under the following conditions:
a. Core clock divider bits CD2, CD1, and CD0 in PLLCON SFR set to 0, 1, and 1, respectively, that is, core clock frequency = 1.57 MHz.
b. SPI bit-rate selection bits SPR1 and SPR0 in SPICON SFR set to 0 and 0, respectively.
SCLOCK Low Pulse Width
SCLOCK High Pulse Width
Data Output Valid After SCLOCK Edge
Data Input Setup Time Before SCLOCK Edge
Data Input Hold Time After SCLOCK Edge
Data Output Fall Time
Data Output Rise Time
SCLOCK Rise Time
SCLOCK Fall Time
(CPOL = 0)
(CPOL = 1)
SCLOCK
SCLOCK
MOSI
MISO
1
1
t
DAV
t
SH
t
DSU
Figure 76. SPI Master Mode Timing (CHPA = 1)
MSB IN
t
MSB
DHD
t
SL
Rev. B | Page 99 of 108
t
DF
t
DR
BITS 6–1
BITS 6–1
t
SR
Min
100
100
ADuC845/ADuC847/ADuC848
t
LSB IN
SF
LSB
Typ
635
635
10
10
10
10
Max
50
25
25
25
25
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns