R0E0200F0EMU00 Renesas Electronics America, R0E0200F0EMU00 Datasheet - Page 72

• Manufacturer Part Number: R0E0200F0EMU00
• Description: EMULATOR E200 MAIN BODY-SH7780
• Manufacturer: Renesas Electronics America
• Series: SuperH®r
• Type: In-Circuit Emulatorr

Specifications of R0E0200F0EMU00

• Contents: Emulator Board, Cables, Software and Documentation
• For Use With/related Products: SH7780
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 1.4 Measurement Items (cont)
Classification
Operand bus
performance
(cont)
46
Type
Access
miss count
(cont)
Waited
cycle
Measurement Item
Number of operand
cache miss (WRITE)
Number of U-RAM
read-buffer miss
Waited cycles for
operand fetch
(READ)
Waited cycles for
operand fetch
(WRITE)
Waited cycles for
operand cache miss
(READ)
Waited cycles for
operand cache miss
(WRITE)
Number of waited
cycles by an I-L
memory access for
operand fetch
(READ)
Number of waited
cycles by an I-L
memory access for
operand fetch
(WRITE)
Option
CMW
UBM
WOR
WOW
WCMR
WCMW
WILR
WILW
Note
The number of cache misses by
an operand cache access (write)
(number of accesses to the
outside of the CPU core due to
a cache miss).
Write-through accesses are not
counted.
Cache misses are not counted
by the PREF instruction.
This function is disabled for the
MPU that the U memory is not
incorporated.
The number of wait cycles by a
memory access (read) of an
operand.
The number of wait cycles by a
memory access (write) of an
operand.
The number of wait cycles by an
operand cache miss (read)
(however, the number of wait
cycles of cache FIII is included
due to contention).
The number of wait cycles by an
operand cache miss (write).
The number of waited cycles by
an I-L memory access (read) of
an operand.
The number of waited cycles by
an I-L memory access (write) of
an operand.