C8051F060-TB Silicon Laboratories Inc, C8051F060-TB Datasheet - Page 280
C8051F060-TB
Manufacturer Part Number
C8051F060-TB
Description
BOARD PROTOTYPING W/C8051F060
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F060-TB
Contents
Board
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F060
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F060/1/2/3/4/5/6/7
23.2.2. 9-Bit UART
9-bit UART mode uses a total of eleven bits per data byte: a start bit, 8 data bits (LSB first), a programma-
ble ninth data bit, and a stop bit. The state of the ninth transmit data bit is determined by the value in TB81
(SCON1.3), which is assigned by user software. It can be assigned the value of the parity flag (bit P in reg-
ister PSW) for error detection, or used in multiprocessor communications. On receive, the ninth data bit
goes into RB81 (SCON1.2) and the stop bit is ignored.
Data transmission begins when an instruction writes a data byte to the SBUF1 register. The TI1 Transmit
Interrupt Flag (SCON1.1) is set at the end of the transmission (the beginning of the stop-bit time). Data
reception can begin any time after the REN1 Receive Enable bit (SCON1.4) is set to ‘1’. After the stop bit
is received, the data byte will be loaded into the SBUF1 receive register if the following conditions are met:
(1) RI1 must be logic 0, and (2) if MCE1 is logic 1, the 9th bit must be logic 1 (when MCE1 is logic 0, the
state of the ninth data bit is unimportant). If these conditions are met, the eight bits of data are stored in
SBUF1, the ninth bit is stored in RB81, and the RI1 flag is set to ‘1’. If the above conditions are not met,
SBUF1 and RB81 will not be loaded and the RI1 flag will not be set to ‘1’. A UART1 interrupt will occur if
enabled when either TI1 or RI1 is set to ‘1’.
Figure 23.5. 9-Bit UART Timing Diagram
MARK
START
STOP
D0
D1
D2
D3
D4
D5
D6
D7
D8
BIT
BIT
SPACE
BIT TIMES
BIT SAMPLING
280
Rev. 1.2
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