C8051F060-TB Silicon Laboratories Inc, C8051F060-TB Datasheet - Page 278
![BOARD PROTOTYPING W/C8051F060](/photos/28/94/289414/tqfp-100_sml.jpg)
C8051F060-TB
Manufacturer Part Number
C8051F060-TB
Description
BOARD PROTOTYPING W/C8051F060
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F060-TB
Contents
Board
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F060
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
- Current page: 278 of 328
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C8051F060/1/2/3/4/5/6/7
23.1. Enhanced Baud Rate Generation
The UART1 baud rate is generated by Timer 1 in 8-bit auto-reload mode. The TX clock is generated by
TL1; the RX clock is generated by a copy of TL1 (shown as RX Timer in Figure 23.2), which is not user-
accessible. Both TX and RX Timer overflows are divided by two to generate the TX and RX baud rates.
The RX Timer runs when Timer 1 is enabled, and uses the same reload value (TH1). However, an
RX Timer reload is forced when a START condition is detected on the RX pin. This allows a receive to
begin any time a START is detected, independent of the TX Timer state.
Timer 1 should be configured for Mode 2, 8-bit auto-reload (see
Timer with Auto-Reload” on page
at two times the desired baud rate. Note that Timer 1 may be clocked by one of five sources: SYSCLK,
SYSCLK / 4, SYSCLK / 12, SYSCLK / 48, or the external oscillator clock / 8. For any given Timer 1 clock
source, the UART1 baud rate is determined by Equation 23.1.
Where T1
value). Timer 1 clock frequency is selected as described in
page
through Table 23.6. Note that the internal oscillator may still generate the system clock when the external
oscillator is driving Timer 1 (see
278
287. A quick reference for typical baud rates and system clock frequencies is given in Table 23.1
CLK
is the frequency of the clock supplied to Timer 1, and T1H is the high byte of Timer 1 (reload
Detected
Start
RX Timer
Section “24.1. Timer 0 and Timer 1” on page 287
UartBaudRate
Figure 23.2. UART1 Baud Rate Logic
289). The Timer 1 reload value should be set so that overflows will occur
Timer 1
TH1
TL1
Equation 23.1. UART1 Baud Rate
Overflow
Overflow
Rev. 1.2
=
------------------------------ -
256 T1H
T1
–
CLK
Section “24.1. Timer 0 and Timer 1” on
2
2
Section “24.1.3. Mode 2: 8-bit Counter/
UART1
1
-- -
2
RX Clock
TX Clock
for more details).
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