C8051F120-TB Silicon Laboratories Inc, C8051F120-TB Datasheet - Page 83

BOARD PROTOTYPING W/C8051F120

C8051F120-TB

Manufacturer Part Number
C8051F120-TB
Description
BOARD PROTOTYPING W/C8051F120
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheets

Specifications of C8051F120-TB

Contents
Board
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Kit Contents
Board
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051F120-TB
Manufacturer:
Silicon Labs
Quantity:
135
VREF x (1023/1024)
VREF x (511/1024)
VREF x (511/512)
10-bit ADC0 Data Word appears in the ADC0 Data Word Registers as follows:
ADC0H[1:0]:ADC0L[7:0], if AD0LJST = 0
=
ADC0H[7:0]:ADC0L[7:6], if AD0LJST = 1
Example: ADC0 Data Word Conversion Map, AIN0.0 Input in Single-Ended Mode
Example: ADC0 Data Word Conversion Map, AIN0.0-AIN0.1 Differential Input Pair
For AD0LJST = 0:
Code
–VREF x (1/512)
VREF x (1/512)
AIN0.0–AIN0.1
AIN0.0–AGND
–VREF / 2
VREF / 2
VREF / 2
–VREF
(Volts)
(Volts)
=
0
0
(ADC0H[7:2] will be sign-extension of ADC0H.1 for a differential reading, otherwise
000000b).
(ADC0L[5:0] = 00b).
(AMX0CF = 0x00, AMX0SL = 0x00)
(AMX0CF = 0x01, AMX0SL = 0x00)
Vin
Figure 6.5. ADC0 Data Word Example
-------------- -
VREF
Gain
ADC0H:ADC0L
ADC0H:ADC0L
0xFF00 (–256d)
0xFE00 (–512d)
(AD0LJST = 0)
(AD0LJST = 0)
0xFFFF (–1d)
0x03FF
0x01FF
0x0000
0x01FF
0x0000
0x0200
0x0100
0x0001
2
n
; ‘n’ = 10 for Single-Ended; ‘n’= 9 for Differential.
Rev. 1.4
C8051F120/1/2/3/4/5/6/7
ADC0H:ADC0L
ADC0H:ADC0L
(AD0LJST = 1)
(AD0LJST = 1)
0xFFC0
0x7FC0
0xFFC0
0x7FC0
0xC000
0x8000
0x0000
0x4000
0x0040
0x0000
0x8000
C8051F130/1/2/3
83

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