C8051F120-TB Silicon Laboratories Inc, C8051F120-TB Datasheet - Page 265
C8051F120-TB
Manufacturer Part Number
C8051F120-TB
Description
BOARD PROTOTYPING W/C8051F120
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F120-TB
Contents
Board
Processor To Be Evaluated
C8051F12x and C8051F13x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F120
Silicon Family Name
C8051F12x
Kit Contents
Board
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F120
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F120-TB
Manufacturer:
Silicon Labs
Quantity:
135
- Current page: 265 of 350
- Download datasheet (2Mb)
C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
Setting the SMBus0 Free Timer Enable bit (FTE, SMB0CN.1) to logic 1 enables the timer in SMB0CR.
When SCL goes high, the timer in SMB0CR counts up. A timer overflow indicates a free bus timeout: if
SMBus0 is waiting to generate a START, it will do so after this timeout. The bus free period should be less
than 50 µs (see SFR Definition 19.2, SMBus0 Clock Rate Register).
When the TOE bit in SMB0CN is set to logic 1, Timer 3 is used to detect SCL low timeouts. If Timer 3 is
enabled (see
Section “23.2. Timer 2, Timer 3, and Timer 4” on page 317
), Timer 3 is forced to reload
when SCL is high, and forced to count when SCL is low. With Timer 3 enabled and configured to overflow
after 25 ms (and TOE set), a Timer 3 overflow indicates a SCL low timeout; the Timer 3 interrupt service
routine can then be used to reset SMBus0 communication in the event of an SCL low timeout.
Rev. 1.4
265
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