C8051F120-TB Silicon Laboratories Inc, C8051F120-TB Datasheet - Page 336

• Manufacturer Part Number: C8051F120-TB
• Description: BOARD PROTOTYPING W/C8051F120
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120-TB

• Contents: Board
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Kit Contents: Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
336
Bit7:
Bits6–4: UNUSED. Read = 000b, Write = don't care.
Bits3–1: CPS2-CPS0: PCA0 Counter/Timer Pulse Select.
Bit0:
CIDL
R/W
Bit7
CIDL: PCA0 Counter/Timer Idle Control.
Specifies PCA0 behavior when CPU is in Idle Mode.
0: PCA0 continues to function normally while the system controller is in Idle Mode.
1: PCA0 operation is suspended while the system controller is in Idle Mode.
These bits select the timebase source for the PCA0 counter
ECF: PCA Counter/Timer Overflow Interrupt Enable.
This bit sets the masking of the PCA0 Counter/Timer Overflow (CF) interrupt.
0: Disable the CF interrupt.
1: Enable a PCA0 Counter/Timer Overflow interrupt request when CF (PCA0CN.7) is set.
CPS2
0
0
0
0
1
1
1
1
R/W
Bit6
-
CPS1
0
0
1
1
0
0
1
1
SFR Definition 24.2. PCA0MD: PCA0 Mode
R/W
Bit5
-
CPS0
0
1
0
1
0
1
0
1
R/W
Bit4
System clock divided by 12
System clock divided by 4
Timer 0 overflow
High-to-low transitions on ECI (max rate = system clock
divided by 4)
System clock
External clock divided by 8 (synchronized with system clock)
Reserved
Reserved
-
Rev. 1.4
CPS2
R/W
Bit3
CPS1
R/W
Bit2
Timebase
CPS0
R/W
Bit1
SFR Address:
SFR Page:
ECF
R/W
Bit0
0xD9
0
00000000
Reset Value