C8051F120-TB Silicon Laboratories Inc, C8051F120-TB Datasheet - Page 246

• Manufacturer Part Number: C8051F120-TB
• Description: BOARD PROTOTYPING W/C8051F120
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F120-TB

• Contents: Board
• Processor To Be Evaluated: C8051F12x and C8051F13x
• Interface Type: USB
• Silicon Manufacturer: Silicon Labs
• Core Architecture: 8051
• Silicon Core Number: C8051F120
• Silicon Family Name: C8051F12x
• Kit Contents: Board
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F120
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F120/1/2/3/4/5/6/7
C8051F130/1/2/3
246
Bit7:
Bit6:
Bit5:
Bit4:
Bit3:
Bit2:
Bit1:
Bit0:
SYSCKE
R/W
Bit7
SYSCKE: /SYSCLK Output Enable Bit.
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK (divided by 1, 2, 4, or 8) routed to Port pin. divide factor is determined by the
CLKDIV1–0 bits in register CLKSEL (See
T2EXE: T2EX Input Enable Bit.
0: T2EX unavailable at Port pin.
1: T2EX routed to Port pin.
T2E: T2 Input Enable Bit.
0: T2 unavailable at Port pin.
1: T2 routed to Port pin.
INT1E: /INT1 Input Enable Bit.
0: /INT1 unavailable at Port pin.
1: /INT1 routed to Port pin.
T1E: T1 Input Enable Bit.
0: T1 unavailable at Port pin.
1: T1 routed to Port pin.
INT0E: /INT0 Input Enable Bit.
0: /INT0 unavailable at Port pin.
1: /INT0 routed to Port pin.
T0E: T0 Input Enable Bit.
0: T0 unavailable at Port pin.
1: T0 routed to Port pin.
CP1E: CP1 Output Enable Bit.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
T2EXE
SFR Definition 18.2. XBR1: Port I/O Crossbar Register 1
R/W
Bit6
T2E
R/W
Bit5
INT1E
R/W
Bit4
Rev. 1.4
T1E
R/W
Bit3
Section “14. Oscillators” on page 185
INT0E
R/W
Bit2
T0E
R/W
Bit1
SFR Address:
SFR Page:
CP1E
R/W
Bit0
0xE2
F
00000000
Reset Value
).