C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 30

• Manufacturer Part Number: C8051F320-TB
• Description: BOARD PROTOTYPING W/C8051F320
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F320-TB

• Contents: Board
• Processor To Be Evaluated: C8051F320/F321
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F320
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F320/1
4.
30
CNVSTR
REGIN
XTAL1
XTAL2
Pinout and Package Definitions
Name
VBUS
/RST/
C2CK
VREF
P3.0/
P0.2/
P0.3/
P0.6/
P0.7/
GND
VDD
P0.0
P0.1
P0.4
P0.5
P1.0
C2D
D+
D-
Pin Numbers
‘F320
10
32
31
30
29
28
27
26
6
3
9
7
8
4
5
2
1
Table 4.1. Pin Definitions for the C8051F320/1
‘F321
10
28
27
26
25
24
23
22
6
3
9
7
8
4
5
2
1
Power In
Power In 5 V Regulator Input. This pin is the input to the on-chip volt-
A I/O or
D I/O or
Power
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
D I/O
A I/O
Type
D In
D In
A In
A In
Out
Description
2.7-3.6 V Power Supply Voltage Input.
3.3 V Voltage Regulator Output. See Section 8.
Ground.
Device Reset. Open-drain output of internal POR or VDD
monitor. An external source can initiate a system reset by
driving this pin low for at least 15 µs. See Section 10.
Clock signal for the C2 Debug Interface.
Port 3.0. See Section 14 for a complete description.
Bi-directional data signal for the C2 Debug Interface.
age regulator.
VBUS Sense Input. This pin should be connected to the
VBUS signal of a USB network. A 5 V signal on this pin indi-
cates a USB network connection.
USB D+.
USB D–.
Port 0.0. See Section 14 for a complete description of Port 0.
Port 0.1.
Port 0.2.
External Clock Input. This pin is the external oscillator return
for a crystal or resonator. See Section 13.
Port 0.3.
External Clock Output. This pin is the excitation driver for an
external crystal or resonator, or an external clock input for
CMOS, capacitor, or RC oscillator configurations. See Sec-
tion 13.
Port 0.4.
Port 0.5.
Port 0.6.
ADC0 External Convert Start Input. See Section 5.
Port 0.7.
External VREF input or output. See Section 6.
Port 1.0. See Section 14 for a complete description of Port 1.
Rev. 1.4