C8051F320-TB Silicon Laboratories Inc, C8051F320-TB Datasheet - Page 100
C8051F320-TB
Manufacturer Part Number
C8051F320-TB
Description
BOARD PROTOTYPING W/C8051F320
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Specifications of C8051F320-TB
Contents
Board
Processor To Be Evaluated
C8051F320/F321
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F320
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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C8051F320/1
10.1. Power-On Reset
During power-up, the device is held in a reset state and the /RST pin is driven low until VDD settles above
V
typically less than 0.3 ms. Figure 10.2. plots the power-on and VDD monitor reset timing.
On exit from a power-on reset, the PORSF flag (RSTSRC.1) is set by hardware to logic 1. When PORSF is
set, all of the other reset flags in the RSTSRC Register are indeterminate (PORSF is cleared by all other
resets). Since all resets cause program execution to begin at the same location (0x0000) software can
read the PORSF flag to determine if a power-up was the cause of reset. The content of internal data mem-
ory should be assumed to be undefined after a power-on reset. The VDD monitor is enabled following a
power-on reset.
Software can force a power-on reset by writing ‘1’ to the PINRSF bit in register RSTSRC.
100
RST
. A Power-On Reset delay (T
Logic HIGH
Figure 10.2. Power-On and VDD Monitor Reset Timing
Logic LOW
2.70
2.4
2.0
1.0
/RST
V
PORDelay
RST
Power-On
Reset
) occurs before the device is released from reset; this delay is
T
PORDelay
Rev. 1.4
Monitor
Reset
VDD
VDD
t
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