Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 298

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
Power Failure Protection
Optimizing NVDS Memory Usage for Execution Speed
The NVDS routines employ error checking mechanisms to ensure a power failure endan-
gers only the most recently written byte. Bytes previously written to the array are not per-
turbed. For this protection to function, the VBO must be enabled (see
on page 45) and configured for a threshold voltage of 2.4 V or greater (see
Address Space
A System Reset (such as a pin reset or watchdog timer reset) that occurs during a write
operation also perturbs the byte currently being written. All other bytes in the array are
unperturbed.
As listed in
trade-off for minimizing the frequency of writes that require post-write page erases. The
NVDS read time of address N is a function of the number of writes to addresses other than
N since the most recent write to address N, as well as the number of writes since the most
recent page erase. Neglecting effects caused by page erases and results caused by the
initial condition in which the NVDS is blank, a rule of thumb is that every write since the
most recent page erase causes read times of unwritten addresses to increase by 0.8 s, up
to a maximum of 258 s.
If NVDS read performance is critical to your software architecture, you can optimize your
code for speed by using either of the methods listed below.
1. Periodically refresh all addresses that are used. This is the most useful method. The
2. Use as few unique addresses as possible. This helps to optimize the impact of
optimal use of NVDS in terms of speed is to rotate the writes evenly among all
addresses planned to use, bringing all reads closer to the minimum read time. Because
the minimum read time is much less than the write time, however, actual speed
benefits are not always realized.
refreshing.
Table 161.NVDS Read Time
Operation
Read
Write
Illegal Read
Illegal Write
Table
on page 272).
161, the NVDS read time varies drastically, this discrepancy being a
P R E L I M I N A R Y
Minimum
Latency (
71
126
6
7
s
)
Maximum
Latency (
258
6
7
136
Z8 Encore! XP
s
)
Product Specification
Non-Volatile Data Storage
Low-Power Modes
®
F1680 Series
Trim Bit
284