Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 240

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

PS025011-1010
S
Slave Address
1st Byte
Figure 46. Data Transfer Format—Master Read Transaction with a 10-Bit Address
2. The software writes the I
3. The software asserts the
4. If this operation is a single-byte transfer, the software asserts the NAK bit of 
5. The I
6. The I
7. The I
8. The I
9. The I
10. The software responds by reading the I
11. The I
12. If there are more bytes to transfer, the I
13. A NAK interrupt (
14. The software responds by setting the STOP bit of the I
15. A
Master Read Transaction with a 10-Bit Address
Figure 46
this mode when addressed as a slave (but not for the remote slave). The software
asserts the IEN bit in the I
Read bit (which is set to 1).
the I
the I
next high period of SCL.
If the slave does not acknowledge the address byte, the I
bit in the I
Register. The software responds to the Not Acknowledge interrupt by setting the
bit and clearing the
sends a
is complete, and the following steps can be ignored.
the final byte, the software must set the
final byte; otherwise, it sends an Acknowledge.
W=0 A
STOP
2
2
2
2
2
2
2
2
C Control Register so that after the first byte of data has been read by 
C controller, a Not Acknowledge instruction is sent to the I
displays the read transaction format for a 10-bit addressed Slave.
C controller sends a
C controller sends the address and Read bit out via the SDA signal.
C slave acknowledges the address by pulling the SDA signal Low during the
C controller shifts in the first byte of data from the I
C controller asserts the receive interrupt.
C controller sends a Not Acknowledge to the I
STOP
condition is sent to the I
2
Slave Address
C Status Register, sets the
condition on the bus, and clears the
2nd Byte
NCKI
TXI
P R E L I M I N A R Y
bit. The I
bit in I2CISTAT) is generated by the I
START
2
C Data Register with a 7-bit slave address, plus the 
2
START
A S
C Control Register.
bit of the I
2
C slave.
2
Slave Address
condition.
C controller flushes the Transmit Data Register,
1st Byte
ACKV
2
2
C Data Register. If the next data byte is to be
NAK
C controller returns to
2
C Control Register.
bit, and clears the
bit of the I
STOP
R=1
Z8 Encore! XP
2
C slave if the next byte is the
2
and
2
C Control Register.
C Control Register.
2
A
C controller sets the NCKI
2
C slave on the SDA signal.
NCKI
Product Specification
I2C Master/Slave Controller
Data
ACK
2
Step
C controller.
2
bits. The transaction
C slave.
bit in the I
7.
A
®
F1680 Series
Data
2
C State
STOP
A P
226