Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 210
![KIT DEV FOR Z8F642 MCU 44 PIN](/photos/9/25/92529/z8f16800144zcog_sml.jpg)
Z8F16800144ZCOG
Manufacturer Part Number
Z8F16800144ZCOG
Description
KIT DEV FOR Z8F642 MCU 44 PIN
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Specifications of Z8F16800144ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F642
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4678
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PS025011-1010
Input Sample Time
(CLKPOL = 0)
(CLKPOL = 1)
Transfer Format when Phase Equals Zero
Figure 34
For SPI transfers the clock only toggles during the character transfer. The two SCK
waveforms show polarity with CLKPOL = 0 and CLKPOL = 1. The diagram may be
interpreted as either a Master or Slave timing diagram because the SCK Master-In/
Slave-Out (MISO) and Master-Out/Slave-In (MOSI) pins are directly connected between
the Master and the Slave.
Transfer Format When Phase Equals One
Figure 35
PHASE is one. For SPI transfers the clock only toggles during the character transfer. Two
waveforms are depicted for SCK, one for CLKPOL = 0 and another for CLKPOL = 1.
MOSI
MISO
SCK
SCK
SS
displays the timing diagram for an SPI type transfer, in which PHASE=0.
on page 197 displays the timing diagram for an SPI type transfer in which
Bit7
Bit7
Figure 34. ESPI Timing when PHASE = 0
Bit6
Bit6
P R E L I M I N A R Y
Bit5
Bit5
Bit4
Bit4
Bit3
Bit3
Bit2
Bit2
Z8 Encore! XP
Enhanced Serial Peripheral Interface
Bit1
Bit1
Product Specification
Bit0
Bit0
®
F1680 Series
196
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