Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 118
Z8F16800144ZCOG
Manufacturer Part Number
Z8F16800144ZCOG
Description
KIT DEV FOR Z8F642 MCU 44 PIN
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Specifications of Z8F16800144ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F642
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4678
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PS025011-1010
Table 51. DEMODULATION Mode Initialization Example (Continued)
Register
T0PWM1H
T0PWM1H
T0NFC
PAADDR
PACTL[1:0]
IRQ0ENH[5]
IRQ0ENL[5]
T0CTL1
Notes: After receiving the input trigger (rising or falling edge), Timer 0 will:
Reading the Timer Count Values
Timer Output Signal Operation
Timer Noise Filter
1. Start counting on timer clock.
2. Upon receiving a Timer 0 Input rising edge, save Capture value in T0PWM0
3. Upon receiving a Timer 0 Input falling edge, save Capture value in T0PWM1 registers,
4. After timer count to ABCD clocks, set reload event flag, and reset Timer count to start value.
registers, generate interrupt, and continue to count.
generate interrupt, and continue to count.
The current count value in the timers can be read while counting (enabled). This capability
has no effect on timer operation. When the timer is enabled and the Timer High Byte
register is read, the contents of the Timer Low Byte register are placed in a holding
register. A subsequent read from the Timer Low Byte register returns the value in the
holding register. This operation allows accurate reads of the full 16-bit timer count value
while enabled. When the timers are not enabled, a read from the Timer Low Byte register
returns the actual value in the counter.
Timer Output is a GPIO Port pin alternate function. Generally, the Timer Output is toggled
every time the counter is reloaded.
A Noise Filter circuit is included which filters noise on a Timer Input signal before the
data is sampled by the block.
C0H
Value
00H
00H
02H
11B
0B
0B
84H
Comment
Initial PWM1 value = 0000H
NFEN = 1 enables noise filter
NFCTL = 100B enables 8-bit up/down counter
Selects Port A Alternate Function control register.
PACTL[0] enables Timer 0 Input alternate function.
PACTL[1] enables Timer 0 Output alternate function.
Disables the Timer 0 interrupt.
TEN = 1 enables the timer. All other bits left in desired settings.
P R E L I M I N A R Y
Z8 Encore! XP
Product Specification
®
F1680 Series
Timers
104
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