Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 252

• Manufacturer Part Number: Z8F16800144ZCOG
• Description: KIT DEV FOR Z8F642 MCU 44 PIN
• Manufacturer: Zilog
• Series: Z8 Encore!®r
• Type: MCUr

Specifications of Z8F16800144ZCOG

• Contents: Hardware, Software and Documentation
• For Use With/related Products: Z8F642
• For Use With: 269-4661 - KIT ACC ETHERNET SMART CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 269-4678

Table 122. I
PS025011-1010
BITS
FIELD
RESET
R/W
ADDR
Note:
2
C Control Register (I2CCTL)
R/W
IEN
7
0

The R/W1 bit may be set (written to 1), when IEN = 1, but cannot be cleared
(written 1 or 0) anyway.
IEN—I
This bit enables the I
START—Send
When set, this bit causes the I
START
the
writing to the bit. After this bit is set, a
I2CDATA or I
controller waits until data is loaded. If this bit is set while the I
data, it generates a
completes. If the
START
device, the START bit will be cleared and ARBLST bit in the Interrupt Status Register
will be set.
STOP—Send
When set, this bit causes the I
STOP
a byte is received in a receive operation. When set, this bit is reset by the I
after a
be cleared to 0 by writing to the register. If STOP is set while a SLAVE mode transaction
is underway, the STOP bit is cleared by hardware.
BIRQ—Baud Rate Generator Interrupt Request
This bit is ignored when the I
controller is disabled (
causing an interrupt to occur every time the baud rate generator counts down to one. The
baud rate generator runs continuously in this mode, generating periodic interrupts.
TXI—Enable TDRE interrupts
This bit enables interrupts when the I
START
condition after the byte in the I
STOP
condition. After it is asserted, this bit is cleared by the I
condition. If START is set while a SLAVE mode transaction is underway to this
2
START
C Enable
R/W1
condition or by deasserting the
6
0
condition has been sent or by deasserting the
2
STOP
C Shift Register. If there is no data in one of these registers, the I
START
STOP
RESTART
2
condition
STOP
R/W1
C controller.
IEN
5
0
bit is also set, it waits till the
condition
= 0), the baud rate generator is used as an additional timer
P R E L I M I N A R Y
condition after the byte shifts and the Acknowledge phase
2
2
2
C controller is enabled. If this bit is set = 1 when the I
C controller (when configured as the master) to send a
C controller (when configured as the master) to send the
BIRQ
R/W
4
0
2
2
C Shift Register has completed transmission or after
C Data Register is empty.
F52H
START
IEN
R/W
TXI
condition is sent if there is data in the
bit. If this bit is 1, it cannot be cleared by
3
0
STOP
Z8 Encore! XP
R/W1
NAK
IEN
condition is sent before the
2
0
2
bit. If this bit is 1, it cannot
2
C controller is shifting out
C controller after it sends
Product Specification
I2C Master/Slave Controller
FLUSH
W
1
0
®
2
F1680 Series
C controller

2
FILTEN
C
R/W
0
0
2
C
238