Z8F16800144ZCOG Zilog, Z8F16800144ZCOG Datasheet - Page 215
Z8F16800144ZCOG
Manufacturer Part Number
Z8F16800144ZCOG
Description
KIT DEV FOR Z8F642 MCU 44 PIN
Manufacturer
Zilog
Series
Z8 Encore!®r
Type
MCUr
Specifications of Z8F16800144ZCOG
Contents
Hardware, Software and Documentation
For Use With/related Products
Z8F642
For Use With
269-4661 - KIT ACC ETHERNET SMART CABLE
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
269-4678
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PS025011-1010
Figure 40. ESPI Configured as an SPI Master in a Single Master, Multiple Slave System
Figure 39. ESPI Configured as an SPI Master in a Single Master, Single Slave System
To Slave #2’s SS Pin
To Slave #1’s SS Pin
To Slave’s SS Pin
Multi-Master SPI Operation
In a Multi-Master SPI system, all SCK pins are tied together, all MOSI pins are tied
together, and all MISO pins are tied together. All SPI pins must be configured in
open-drain mode to prevent bus contention. At any time, only one SPI device is
configured as the Master and all other devices on the bus are configured as slaves. The
Master asserts the SS pin on the selected slave. Then, the active Master drives the clock
and transmits data on the SCK and MOSI pins to the SCK and MOSI pins on the Slave
(including those Slaves which are not enabled). The enabled slave drives data out its
MISO pin to the MISO Master pin.
From Slave
From Slaves
To Slave
To Slave
To Slaves
To Slaves
MISO
MOSI
SCK
SS
P R E L I M I N A R Y
MISO
MOSI
SCK
GPIO
GPIO
Bit 0
Bit 0
8-bit Shift Register
8-bit Shift Register
ESPI Master
ESPI Master
Bit 7
Baud Rate
Generator
Bit 7
Baud Rate
Generator
Z8 Encore! XP
Enhanced Serial Peripheral Interface
Product Specification
®
F1680 Series
201
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