EVAL-ADUC7023QSPZ1 Analog Devices Inc, EVAL-ADUC7023QSPZ1 Datasheet - Page 77

• Manufacturer Part Number: EVAL-ADUC7023QSPZ1
• Description: BOARD EVAL FOR ADUC7023
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7023QSPZ1

• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7023
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

FIQSTA
FIQSTA is a read-only register that provides the current enabled
FIQ source status (effectively a logic AND of the FIQSIG and
FIQEN bits). When set to 1, that source generates an active FIQ
request to the ARM7TDMI core. There is no priority encoder
or interrupt vector generation. This function is implemented in
software in a common interrupt handler routine.
FIQSTA Register
Name:
Address:
Default value:
Access:
Programmed Interrupts
Because the programmed interrupts are not maskable, they are
controlled by another register (SWICFG) that writes into both
IRQSTA and IRQSIG registers and/or the FIQSTA and FIQSIG
registers at the same time.
The 32-bit register dedicated to software interrupt is SWICFG
described in Table 88. This MMR allows the control of a
programmed source interrupt.
Table 88. SWICFG MMR Bit Designations
Bit
31 to 3
2
1
0
Any interrupt signal must be active for at least the minimum
interrupt latency time, to be detected by the interrupt controller
and to be detected by the user in the IRQSTA and FIQSTA
registers.
IRQ_SOURCE
FIQ_SOURCE
BIT 31 TO
UNUSED
Description
Reserved.
Programmed interrupt FIQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of FIQSTA and
FIQSIG.
Programmed interrupt IRQ. Setting/clearing this bit
corresponds to setting/clearing Bit 1 of IRQSTA and
IRQSIG.
Reserved.
BIT 23
PER INTERRUPT (IRQP0/IRQP1/IRQP2)
PROGRAMMABLE PRIORITY
FIQSTA
0x00000000
Read only
0xFFFF0100
BIT 22 TO BIT 7
INTERRUPT VECTOR
(IRQBASE)
Figure 41. Interrupt Structure
INTERNAL
ARBITER
LOGIC
ACTIVE IRQ
PRIORITY
HIGHEST
BIT 6 TO
BIT 2
BIT 1 TO
BIT 0
LBSs
POINTER TO
FUNCTION
(IRQVEC)
Rev. B | Page 77 of 96
VECTORED INTERRUPT CONTROLLER (VIC)
The ADuC7023 incorporates an enhanced interrupt control
system or vectored interrupt controller. The vectored interrupt
controller for IRQ interrupt sources is enabled by setting Bit 0
of the IRQCONN register. Similarly, Bit 1 of IRQCONN enables
the vectored interrupt controller for the FIQ interrupt sources.
The vectored interrupt controller provides the following
enhancements to the standard IRQ/FIQ interrupts:
•
•
•
VIC MMRs
IRQBASE Register
The vector base register, IRQBASE, is used to point to the start
address of memory used to store 32 pointer addresses. These
pointer addresses are the addresses of the individual interrupt
service routines.
Name:
Address:
Default value:
Access:
Table 89. IRQBASE MMR Bit Designations
Bit
31:16
15:0
Vectored interrupts allow a user to define separate
interrupt service routine addresses for every interrupt
source. This is achieved by using the IRQBASE and
IRQVEC registers.
IRQ/FIQ interrupts can be nested up to eight levels
depending on the priority settings. An FIQ still has a
higher priority than an IRQ. Therefore, if the VIC is
enabled for both the FIQ and IRQ and prioritization is
maximized, then it is possible to have 16 separate interrupt
levels.
Programmable interrupt priorities, using the IRQP0 to
IRQP2 registers, can be assigned an interrupt priority level
value between 0 and 7.
Type
Read only
R/W
IRQBASE
0xFFFF0014
0x00000000
Read and write
Initial Value
Reserved
0
Always read as 0.
Vector base address.
Description
ADuC7023