EVAL-ADUC7023QSPZ1 Analog Devices Inc, EVAL-ADUC7023QSPZ1 Datasheet - Page 30

• Manufacturer Part Number: EVAL-ADUC7023QSPZ1
• Description: BOARD EVAL FOR ADUC7023
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7023QSPZ1

• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7023
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC7023
Bit
7
6
5
4 to 3
2 to 0
ADCCP Register
Name:
Address:
Default value:
Access:
Function:
Table 25. ADCCP MMR Bit Designation
Bit
7 to 5
4 to 0
Value
00000
00001
00010
00011
00100
00101
00110
00111
01000
01001
Description
Reserved.
Positive channel selection bits.
ADC0.
ADC1.
ADC2.
ADC3.
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADCCP
0xFFFF0504
0x00
Read/write
ADCCP is an ADC positive channel
selection register. This MMR is described in
Table 25.
Value
00
01
10
11
000
001
010
011
100
101
Other
1
1
1
1
1
1
.
.
.
.
.
.
Description
Enable start conversion.
This bit is set by the user to start any type of conversion command.
This bit is cleared by the user to disable a start conversion (clearing this bit does not stop the ADC
when continuously converting).
Enable the ADC
This bit is set by the user to enable the ADC
This bit is cleared by the user to disable the ADC
ADC power control.
This bit is set by the user to place the ADC in normal mode (the ADC must be powered up for at least
5 μs before it converts correctly).
This bit is cleared by the user to place the ADC in power-down mode.
Conversion mode.
Single-ended mode.
Differential mode.
Pseudo differential mode.
Reserved.
Conversion type.
Enable CONV
Enable Timer1 as a conversion input.
Enable Timer0 as a conversion input.
Single software conversion. This bit is set to 000 after conversion (note that Bit 13 of the ADCCON
MMR should be set before starting a single software conversion to avoid further conversions
triggered by the CONV
Continuous software conversion.
PLA conversion.
Reserved.
START
BUSY
pin as a conversion input.
pin.
Rev. B | Page 30 of 96
START
pin).
Bit
1
When a selected ADC channel is shared with one GPIO, by default, this pin is
configured with a weak pull-up resistor enabled. The pull-up resistor should
be disabled manually in the appropriate GPxPAR register. Note the internal
pull-up resistor on P2.0/AIN12 for 40-lead package cannot be disabled.
BUSY
Value
01010
01011
01100
01101
01110
01111
10000
10001
10010
10011
Others
pin.
BUSY
pin.
ADC10
Reserved.
ADC12
Reserved
DAC1
DAC2.
Temperature sensor.
AGND (self-diagnostic feature).
Internal reference (self-diagnostic feature).
AV
Reserved.
Description
DD
/2.
1
1
.
.