EVAL-ADUC7023QSPZ1 Analog Devices Inc, EVAL-ADUC7023QSPZ1 Datasheet - Page 15

• Manufacturer Part Number: EVAL-ADUC7023QSPZ1
• Description: BOARD EVAL FOR ADUC7023
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7023QSPZ1

• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7023
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

40-LFCSP
5
6
24
25
26
27
28
17
18
19
20
23
Pin No.
32-LFCSP
5
6
20
21
22
23
24
13
14
15
16
19
Mnemonic
DAC2
DAC3
TMS
P0.0/nTRST/ADC
P0.1/PLAI[9]/TDO
P0.2/PLAO[8]/TDI
P0.3/PLAO[9]/TCK
DGND
IOV
LV
RST
RTCK
DD
DD
BUSY
/PLAI[8]/BM
Rev. B | Page 15 of 96
This is a multifunction pin as follows:
Digital Ground.
Description
DAC2 Voltage Output or ADC Input.
DAC3 Voltage Output or ADC Input.
Test Mode Select, JTAG Test Port Input. Debug and download access.
This pin has an internal pull-up resistor to IOV
pull-up resistor is also required to ensure the part does not enter an
erroneous state.
General-Purpose Input and Output Port 0.0. By default, this pin is
configured as GPIO.
JTAG Reset Input. Debug and download access. If this pin is held low, JTAG
access is not possible because the JTAG interface is held in reset and
P0.1/P0.2/P0.3 are configured as GPIO pins.
ADC Busy Signal.
Programmable Logic Array Input Element 8.
Boot Mode Entry Pin. The ADuC7023 enters I
low at reset with a flash address 0x800014 = 0xFFFFFFFFF. The ADuC7023
executes code if BM is pulled high at reset or if BM is low at reset with a
flash address 0x800014 not equal to 0xFFFFFFFFF.
The default value of this pin depends on the level of P0.0/BM. If P0.0/
BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this
pin defaults to a JTAG test data output pin. This is a multifunction pin as
follows:
General-Purpose Input and Output Port 0.1.
Programmable Logic Array Input Element 9.
Test Data Out, JTAG Test Port Output. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code,
and the GP0CON/GP0DAT register bits affecting this pin can not be
changed.
The default value of this pin depends on the level of P0.0/BM. If P0.0/
BM = 0, this pin defaults to a general purpose input. If P0.0/BM = 1, this
pin defaults to a JTAG test data input pin. This is a multifunction pin as
follows:
General-Purpose Input and Output Port 0.2.
Programmable Logic Array Output Element 8.
Test Data In, JTAG Test Port Input. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code,
and the GP0CON/GP0DAT register bits affecting this pin must not be
changed.
The default value of this pin depends on the level of P0.0/BM. If P0.0/BM =
0, this pin defaults to a general purpose input. If P0.0/BM = 1, this pin
defaults to a JTAG test data clock pin. This is a multifunction pin as follows:
General-Purpose Input and Output Port 0.3.
Programmable Logic Array Output Element 9.
Test Clock, JTAG Test Port Clock Input. Debug and download access. When
debugging the part via JTAG, this pin must not be toggled by user code
and the GP0CON/GP0DAT register bits affecting this pin must not be
changed.
3.3 V Supply for GPIO and Input of the On-Chip Voltage Regulator.
2.6 V Output of the On-Chip Voltage Regulator. This output must be
connected to a 0.47 μF capacitor to DGND only.
Reset Input, Active Low.
Return JTAG Clock Signal. This is not the standard JTAG clock signal. It is an
output signal from the JTAG controller. If using a 20-lead JTAG header,
connect to Pin 11.
2
C download mode if BM is
DD
. In some cases an external
ADuC7023