EVAL-ADUC7023QSPZ1 Analog Devices Inc, EVAL-ADUC7023QSPZ1 Datasheet
EVAL-ADUC7023QSPZ1
Specifications of EVAL-ADUC7023QSPZ1
Related parts for EVAL-ADUC7023QSPZ1
EVAL-ADUC7023QSPZ1 Summary of contents
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FEATURES Analog I/O Multichannel, 12-bit, 1 MSPS ADC ADC channels Fully differential and single-ended modes analog input range REF 12-bit voltage output DACs 4 DAC outputs available On-chip voltage reference On-chip temperature sensor ...
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ADuC7023 TABLE OF CONTENTS Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 3 Functional Block Diagram .............................................................. 4 Specifications ..................................................................................... 5 Timing Specifications .................................................................. 8 Absolute Maximum Ratings .......................................................... 13 ESD Caution ................................................................................ 13 Pin ...
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REVISION HISTORY 7/10—Rev Rev. B Changes to Temperature Sensor Parameter in Table 1................. 6 Change to Table 10 and changes to Table 11 ............................... 23 Changes to Table 12 and Table 13 ................................................. 24 Changes to Table 16 ...
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ADuC7023 FUNCTIONAL BLOCK DIAGRAM ADC0 MUX ADC12 ADC2/CMP0 ADC3/CMP1 CMP OUT V REF OSC XCLKI AND PLL XCLKO PSM RST POR ADuC7023 1MSPS 12-BIT ADC 40-LEAD LFCSP TEMP SENSOR VECTORED BAND GAP INTERRUPT REF CONTROLLER ARM7TDMI-BASED MCU WITH ADDITIONAL PERIPHERALS ...
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SPECIFICATIONS AV = IOV = 2 3 2.5 V internal reference REF Table 1. Parameter ADC CHANNEL SPECIFICATIONS ADC Power-Up Time Accuracy Resolution Integral Nonlinearity ...
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ADuC7023 Parameter DAC IN OP AMP MODE DAC Output Buffer in Op Amp Mode Input Offset Voltage Input Offset Voltage Drift Input offset Current Input Bias Current Gain Unity-Gain Frequency CMRR Settling Time Output Slew Rate PSRR DAC AC CHARACTERISTICS ...
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Parameter INTERNAL OSCILLATOR MCU CLOCK RATE From 32 kHz Internal Oscillator From 32 kHz External Crystal Using an External Clock START-UP TIME At Power-On From Pause/Nap Mode From Sleep Mode From Stop Mode PROGRAMMABLE LOGIC ARRAY (PLA) Pin Propagation Delay ...
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ADuC7023 TIMING SPECIFICATIONS 2 Table Timing in Fast Mode (400 kHz) Parameter Description t SCLK low pulse width L t SCLK high pulse width H t Start condition hold time SHD t Data setup time DSU t ...
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Table 4. SPI Master Mode Timing (Phase Mode = 1) Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data input setup time before SCLK edge ...
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ADuC7023 Table 5. SPI Master Mode Timing (Phase Mode = 0) Parameter Description t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data output setup before SCLK edge ...
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Table 6. SPI Slave Mode Timing (Phase Mode = 1) Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t Data ...
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ADuC7023 Table 7. SPI Slave Mode Timing (Phase Mode = 0) Parameter Description SCLK edge SS t SCLK low pulse width SL t SCLK high pulse width SH t Data output valid after SCLK edge DAV t ...
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ABSOLUTE MAXIMUM RATINGS AGND = GND , T = 25°C, unless otherwise noted. REF A Table 8. Parameter AV to IOV DD DD AGND to DGND IOV to DGND AGND DD DD Digital Input Voltage to DGND Digital ...
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ADuC7023 PIN CONFIGURATIONS AND FUNCTION DESCRIPTIONS GND 2 REF DAC0 3 DAC1 4 ADuC7023 DAC2 5 TOP VIEW DAC3 6 P1.4/ADC10/PLAO[3] 7 (Not to Scale) P2.0/ADC12/PWM4/PLAI[ P0.4/IRQ0/SCL0/PLAI[0]/CONV START 10 P0.5/SDA0/PLAI[1]/COMP OUT NOTES 1. THE LFCSP_VQ ...
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Pin No. 40-LFCSP 32-LFCSP Mnemonic 5 5 DAC2 6 6 DAC3 24 20 TMS 25 21 P0.0/nTRST/ADC 26 22 P0.1/PLAI[9]/TDO 27 23 P0.2/PLAO[8]/TDI 28 24 P0.3/PLAO[9]/TCK 17 13 DGND 18 14 IOV RST ...
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ADuC7023 Pin No. 40-LFCSP 32-LFCSP Mnemonic 9 7 P0.4/IRQ0/SCL0/PLAI[0]/CONV 10 8 P0.5/SDA0/PLAI[1]/COMP 11 9 P0.6/MISO/SCL1/PLAI[ P0.7/MOSI/SDA1/PLAO[ XCLKI 22 18 XCLKO 16 N/A P1.7/PWM3/SDA1/PLAI[6] 15 N/A P1.6/PWM2/SCL1/PLAI[5] 29 N/A P1.5/ADC6/PWM 7 N/A P1.4/ADC10/PLAO[ P1.3/ADC5/IRQ3/PLAI[4] 33 ...
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TYPICAL PERFORMANCE CHARACTERISTICS 0.6 0.5 0.4 0.3 0.2 0.1 0 –0.1 –0.2 –0.3 –0.4 0 500 1000 1500 2000 2500 ADC CODES SAMPLING RATE = 950kSPS WORST CASE POSITIVE = 0.63, CODE = 2364 WORST CASE NEGATIVE = –0.46, CODE ...
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ADuC7023 TERMINOLOGY ADC SPECIFICATIONS Integral Nonlinearity (INL) The maximum deviation of any code from a straight line passing through the endpoints of the ADC transfer function. The endpoints of the transfer function are zero scale, a point ½ LSB below ...
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OVERVIEW OF THE ARM7TDMI CORE The ARM7® core is a 32-bit reduced instruction set computer (RISC). It uses a single 32-bit bus for instruction and data. The length of the data can be 8 bits, 16 bits bits. ...
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ADuC7023 More information relative to the model of the programmer and the ARM7TDMI core architecture can be found in ARM7TDMI technical and ARM architecture manuals available directly from ARM Ltd. INTERRUPT LATENCY The worst-case latency for a fast interrupt request ...
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MEMORY ORGANIZATION The ADuC7023 incorporates two separate blocks of memory SRAM and on-chip Flash/EE memory on-chip Flash/EE memory is available to the user, and the remaining 2 kB are reserved for ...
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ADuC7023 0xFFFFFFFF 0xFFFFF820 FLASH CONTROL INTERFACE 0xFFFFF800 0xFFFFF46C GPIO 0xFFFFF400 0xFFFF0FBF PWM 0xFFFF0F80 0xFFFF0B54 PLA 0xFFFF0B00 0xFFFF0A14 SPI 0xFFFF0A00 0xFFFF0948 0xFFFF0900 0xFFFF0848 0xFFFF0800 0xFFFF0620 DAC 0xFFFF0600 0xFFFF0538 ADC 0xFFFF0500 0xFFFF0490 BAND GAP REFERENCE 0xFFFF048C ...
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Table 10. IRQ Address Base = 0xFFFF0000 Address Name Byte Access Type 0x0000 IRQSTA 4 R 0x0004 IRQSIG 4 R 0x0008 IRQEN 4 R/W 0x000C IRQCLR 4 W 0x0010 SWICFG 4 W 0x0014 IRQBASE 4 R/W 0x001C IRQVEC 4 R ...
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ADuC7023 Table 12. Timer Address Base = 0xFFFF0300 Address Name Byte 0x0300 T0LD 2 0x0304 T0VAL 2 0x0308 T0CON 2 0x030C T0CLRI 1 0x0320 T1LD 4 0x0324 T1VAL 4 0x0328 T1CON 4 0x032C T1CLRI 1 0x0330 T1CAP 4 0x0360 T2LD ...
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Address Name Byte Access Type 0x0530 ADCGN 2 R/W 0x0534 ADCOF 2 R/W 0x0544 TSCON 1 R/W 0x0548 TEMPREF 2 R/W Table 16. DAC Address Base = 0xFFFF0600 Address Name 0x0600 DAC0CON 0x0604 DAC0DAT 0x0608 DAC1CON 0x060C DAC1DAT 0x0610 DAC2CON ...
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ADuC7023 Address Name Byte Access Type 0x0914 I2C1MCNT1 1 R 0x0918 I2C1ADR0 1 R/W 0x091C I2C1ADR1 1 R/W 0x0924 I2C1DIV 2 R/W 0x0928 I2C1SCON 2 R/W 0x092C I2C1SSTA 2 R/W 0x0930 I2C1SRX 1 R 0x0934 I2C1STX 1 W 0x0938 I2C1ALT ...
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Table 21. PWM Base Address = 0xFFFF0F80 Address Name Byte Access Type 0x0F80 PWMCON1 2 R/W 0x0F84 PWM0COM0 2 R/W 0x0F88 PWM0COM1 2 R/W 0x0F8C PWM0COM2 2 R/W 0x0F90 PWM0LEN 2 R/W 0x0F94 PWM1COM0 2 R/W 0x0F98 PWM1COM1 2 R/W ...
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ADuC7023 ADC CIRCUIT OVERVIEW The analog-to-digital converter (ADC) incorporates a fast, multichannel, 12-bit ADC. It can operate from 2 3.6 V supplies and is capable of providing a throughput MSPS when the clock source ...
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TYPICAL OPERATION When configured via the ADC control and channel selection registers, the ADC converts the analog input and provides a 12-bit result in the ADC data register. The top four bits are the sign bits. The 12-bit result is ...
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ADuC7023 Bit Value 000 001 010 011 100 101 Other ADCCP Register Name: ADCCP Address: 0xFFFF0504 Default value: 0x00 Access: Read/write Function: ADCCP is an ADC positive ...
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ADCCN Register Name: ADCCN Address: 0xFFFF0508 Default value: 0x01 Access: Read/write Function: ADCCN is an ADC negative channel selection register. This MMR is described in Table 26. Table 26. ADCCN MMR Bit Designation Bit Value Description Reserved. ...
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ADuC7023 ADCGN Register Name: ADCGN Address: 0xFFFF0530 Default value: Factory configured Access: Read/write Function: ADCGN is a 10-bit gain calibration register. ADCOF Register Name: ADCOF Address: 0xFFFF0534 Default value: Factory configured Access: Read/write Function: ADCOF is a 10-bit offset calibration ...
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Single-Ended Mode In single-ended mode, SW2 is always connected internally to ground. The V pin can be floating. The input signal range on IN− IN+ REF CHANNEL+ AIN0 A SW1 ...
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ADuC7023 For system gain error correction, the ADC channel input stage must be tied continuous software ADC REF conversion loop must be implemented to modify the value in ADCGN until the ADCDAT reads Code 4094 to ...
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Table 29. TEMPREF MMR Bit Designations Bit Description Reserved. 8 Temperature reference voltage sign Temperature sensor offset calibration voltage. To calculate the V from the TEMPREF register, TREF perform the following calculation: If TEMPREF ...
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ADuC7023 NONVOLATILE FLASH/EE MEMORY The ADuC7023 incorporates Flash/EE memory technology on chip to provide the user with nonvolatile, in-circuit reprogram- mable memory space. Like EEPROM, flash memory can be programmed in-system at a byte level, although it must first be ...
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SECURITY The Flash/EE memory available to the user can be read and write protected. Bit 31 of the FEEPRO/FEEHIDE MMR (see Table 33) protects the 62 kB from being read through JTAG programming mode. The other 31 ...
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ADuC7023 FEEMOD Register Name: FEEMOD Address: 0xFFFFF804 Default value: 0x0000 Access: Read/write Function: FEEMOD sets the operating mode of the flash control interface. Table 31 shows FEEMOD MMR bit designations. Table 31. FEEMOD MMR Bit Designations Bit Description 15 to ...
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Code Command Description 0x0D Reserved Reserved. 0x0E Reserved Reserved. 0x0F Ping No operation; interrupt generated. 1 The FEECON register always reads 0x07 immediately after execution of any of these commands. FEEDAT Register Name: FEEDAT Address: 0xFFFFF80C Default value: 0xXXXX Access: ...
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ADuC7023 EXECUTION TIME FROM SRAM AND FLASH/EE Execution from SRAM Fetching instructions from SRAM takes one clock cycle because the access time of the SRAM is 2 ns, and a clock cycle minimum. However, if the instruction ...
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REMAP Register Name: REMAP Address: 0xFFFF0220 Default value: 0x00 Access: Read/write Table 35. REMAP MMR Bit Designations Bit Name Description Reserved. 4 Read-only bit. Indicates the size of the Flash/EE memory available. If this bit is set, ...
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ADuC7023 RSTKEY1 Register Name: RSTKEY1 Address: 0xFFFF0248 Default value: 0xXX Access Write RSTKEY2Register Name: RSTKEY2 Address: 0xFFFF0250 Default value: 0xXX Access: Write Table 38. RSTCFG Write Sequence Name RSTKEY1 RSTCFG RSTKEY2 Rev Page Code 0x76 ...
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OTHER ANALOG PERIPHERALS DAC The ADuC7023 incorporates four, 12-bit voltage output DACs on chip. Each DAC has a rail-to-rail voltage output buffer capable of driving 5 kΩ/100 pF. Each DAC has two selectable ranges gap 2.5 ...
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ADuC7023 AV mode only. In 0-to-V mode (with V DD REF lower nonlinearity is similar. However, the upper portion of the transfer function follows the ideal line right to the end (V case, not AV ), showing no signs of ...
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DACBKEY0 Register Name: DACBKEY0 Address: 0xFFFF0650 Default value: 0x0000 Access: Write DACBKEY1 Register Name: DACBKEY1 Address: 0xFFFF0658 Default value: 0x0000 Access: Write Table 43. DACBCFG Write Sequence Name Code DACBKEY0 0x9A DACBCFG User value DACBKEY1 0x0C POWER SUPPLY MONITOR The ...
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ADuC7023 Comparator Interface The comparator interface consists of a 16-bit MMR, CMPCON, which is described in Table 45. CMPCON Register Name: CMPCON Address: 0xFFFF0444 Default value: 0x0000 Access: Read/write Table 45. CMPCON MMR Bit Descriptions Bit Value Name Description 15 ...
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OSCILLATOR AND PLL—POWER CONTROL Clocking System Each ADuC7023 integrates a 32.768 kHz ± 3% oscillator, a clock divider, and a PLL. The PLL locks onto a multiple (1275) of the internal oscillator or an external 32.768 kHz crystal to provide ...
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ADuC7023 MMRs and Keys The operating mode, clocking mode, and programmable clock divider are controlled via three MMRs, PLLCON (see Table 48) and POWCONx. PLLCON controls the operating mode of the clock system, POWCON0 controls the core clock frequency and ...
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Bit Value Name Description CPU clock divider bits. 000 41.78 MHz. 001 20.89 MHz. 010 10.44 MHz. 011 5.22 MHz. 100 2.61 MHz. 101 1.31 MHz. 110 653 kHz. 111 326 kHz. Table 51. POWCON0 Write ...
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ADuC7023 DIGITAL PERIPHERALS GENERAL-PURPOSE INPUT/OUTPUT The ADuC7023 provides general-purpose, bidirectional I/O (GPIO) pins. All I/O pins are 5 V tolerant, meaning the GPIOs support an input voltage general, many of the GPIO pins ...
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GP2PAR Register Name GP2PAR Address 0xFFFFF44C Default value 0x00000000 Access Read/write Function GP2PAR programs the parameters for Port 0, Port 1, and Port 2. Note that the GP2DAT MMR must always be written after changing the GP2PAR MMR. Table 56. ...
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ADuC7023 Bit GP0PAR GP1PAR R(b00) R(b00) 8 R/W R/W 7 Reserved Reserved R(b00) R(b00) 4 R/W R/W 3 Reserved Reserved R(b00) R(b00) 0 R/W R/W 1 When P2.0 is configured as ...
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Table 61. GPxCLR MMR Bit Descriptions Bit Description Reserved Data port x clear bit. This bit is set the user to clear the bit on Port x; this bit also clears ...
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ADuC7023 Table 62. SPISTA MMR Bit Designations Bit Name Description Reserved bits. 11 SPIREX SPI Rx FIFO excess bytes present. This bit is set when there are more bytes in the Rx FIFO than indicated in the ...
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SPIDIV Register Name: SPIDIV Address: 0xFFFF0A0C Default value: 0x00 Access: Read/write Function: This 8-bit MMR is the SPI baud rate selection register. SPI Control Register Name: SPICON Address: 0xFFFF0A10 Default value: 0x0000 Access: Read/write Function: This 16-bit MMR configures the ...
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ADuC7023 Table 63. SPICON MMR Bit Designations Bit Name Description SPIMDE SPI IRQ mode bits. These bits configure when the Tx/Rx interrupts occur in a transfer. [00 interrupt occurs when one byte has been transferred. ...
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Bit Name Description 1 SPIMEN Master mode enable bit. This bit is set by the user to enable master mode. This bit is cleared by the user to enable slave mode. 0 SPIEN SPI enable bit. This bit is set ...
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ADuC7023 The ADuC7023 incorporates two I C peripherals that may configured as a fully I C-compatible I C bus master device fully I C bus-compatible slave device. The two ...
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I C REGISTERS 2 The I C peripheral interfaces consists of a number of MMRs. These are described in the following section Master Registers Master Control Registers, I2CxMCON Name: I2C0MCON, I2C1MCON Address: 0xFFFF0800, ...
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ADuC7023 Master Status Registers, I2CxMSTA Name: I2C0MSTA , I2C1MSTA Address: 0xFFFF0804, 0xFFFF0904 Default value: 0x0000, 0x0000 Access: Read Function: These 16-bit MMRs are the I Table 65. I2CxMSTA MMR Bit Designations Bit Name Description ...
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I C Master Receive Registers, I2CxMRX Name: I2C0MRX, I2C1MRX Address: 0xFFFF0808, 0xFFFF0908 Default value: 0x00 Access: Read only Function: These 8-bit MMRs are the I registers Master Transmit Registers, I2CxMTX Name: I2C0MTX, I2C1MTX Address: 0xFFFF080C 0xFFFF090C ...
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ADuC7023 Address 1 Registers, I2CxADR1 Name: I2C0ADR1, I2C1ADR1 Address: 0xFFFF081C , 0xFFFF091C Default value: 0x00 Access: Read/write Function: These 8-bit MMRs are used in 10-bit addressing mode only. These registers contain the least significant byte of the ...
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Bit Name Description 2 5 I2CSETEN I C early transmit interrupt enable bit. This bit is set to enable a transmit request interrupt just after the positive edge of SCL during the read bit transmission. This bit is cleared to ...
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ADuC7023 Table 72. I2CxSSTA MMR Bit Designations Bit Name Description 15 Reserved bit. 14 I2CSTA This bit is set to 1 if: A start condition followed by a matching address is detected also set if a start byte ...
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Bit Name Description 2 1 I2CSTFE I C slave FIFO underflow status bit. This bit goes high if the Tx FIFO is empty when a master requests data from the slave. This bit is asserted at the rising edge of ...
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ADuC7023 Table 73. I2CxFSTA MMR Bit Designations Bit Name Description Reserved bits. 9 I2CFMTX This bit is set flush the master Tx FIFO. 8 I2CFSTX This bit is set flush the ...
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PLA MMRs Interface The PLA peripheral interface consists of the 22 MMRs described in the following sections. PLAELMx Registers PLAELMx are Element 0 to Element 15 control registers. They configure the input and output mux of each element, select the ...
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ADuC7023 Bit Value 0 PLACLK Register Name: PLACLK Address: 0xFFFF0B40 Default value: 0x00 Access: Read/write Function: PLACLK is the clock selection for the flip- flops. The maximum frequency when using the GPIO pins as the clock input for the PLA ...
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Table 79. Feedback Configuration Bit Value PLAELM0 Element 15 01 Element 2 10 Element 4 11 Element Element 1 01 Element 3 10 Element 5 11 Element 7 PLAADC Register Name: ...
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ADuC7023 PULSE-WIDTH MODULATOR PULSE-WIDTH MODULATOR GENERAL OVERVIEW The ADuC7023 integrates a 5-channel pulse-width modulator (PWM) interface. The PWM outputs can be configured to drive an H-bridge or can be used as standard PWM outputs. On power-up, the PWM outputs default ...
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Table 84. PWMCON1 MMR Bit Designations Bit Name Description 14 SYNC Enables PWM synchronization. Set the user so that all PWM counters are reset on the next clock edge after the detection of a high-to-low transition on ...
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ADuC7023 On power-up, PWMCON1 defaults to 0x0012 (HOFF = 1 and HMODE = 1). All GPIO pins associated with the PWM are configured in PWM mode by default (see Table 85). Clear the PWM trip interrupt by writing any value ...
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PWM0COM0 Compare Register Name: PWM0COM0 Address: 0xFFFF0F84 Default value: 0x0000 Access: Read and write Function: PWM0 output pin goes high when the PWM timer reaches the count value stored in this register. PWM0COM1 Compare Register Name: PWM0COM1 Address: 0xFFFF0F88 Default ...
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ADuC7023 PWM2COM0 Compare Register Name: PWM2COM0 Address: 0xFFFF0FA4 Default value: 0x0000 Access: Read/write Function: PWM4 output pin goes high when the PWM timer reaches the count value stored in this register. PWM2COM1 Compare Register Name: PWM2COM1 Address: 0xFFFF0FA8 Default value: ...
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PROCESSOR REFERENCE PERIPHERALS INTERRUPT SYSTEM There are 22 interrupt sources on the ADuC7023 that are controlled by the interrupt controller. Most interrupts are generated from the on-chip peripherals, such as ADC. Four additional interrupt sources are generated from external interrupt ...
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ADuC7023 IRQEN Register Name: IRQEN Address: 0xFFFF0008 Default value: 0x00000000 Access: Read/write Function: IRQEN provides the value of the current enable mask. When each bit is set to 1, the source request is enabled to create an IRQ exception. When ...
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FIQSTA FIQSTA is a read-only register that provides the current enabled FIQ source status (effectively a logic AND of the FIQSIG and FIQEN bits). When set to 1, that source generates an active FIQ request to the ARM7TDMI core. There ...
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ADuC7023 IRQVEC Register The IRQ interrupt vector register, IRQVEC, points to a memory address containing a pointer to the interrupt service routine of the currently active IRQ. This register should only be read when an IRQ occurs and IRQ interrupt ...
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IRQP0 Register Name: IRQP0 Address: 0xFFFF0020 Default value: 0x00000000 Access: Read and write Table 91. IRQP0 MMR Bit Designations Bit Name Description 31 Reserved Reserved bit PLLPI A priority level can be set ...
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ADuC7023 IRQCONN Register The IRQCONN register is the IRQ and FIQ control register. It contains two active bits. The first to enable nesting and prioritization of IRQ interrupts and the other to enable nesting and prioritization of FIQ interrupts. If ...
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To clear a bit in this register, all bits of a higher priority must be cleared first only possible to clear one bit at a time. For example, if this register is set to 0x09, then writing 0xFF ...
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ADuC7023 Table 99. IRQCLRE MMR Bit Designations Bit Name Description 31 to Reserved These bits are reserved and should not be 21 written to. 20 PLA1CLRI A 1 must be written to this bit in the PLA IRQ1 interrupt service ...
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T0CON Register Name: T0CON Address: 0xFFFF0308 Default value: 0x0000 Access: R/W T0CON is the configuration MMR described in Table 100. Table 100. T0CON MMR Bit Descriptions Bit Value Description Reserved. 7 Timer0 enable bit. This bit is ...
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ADuC7023 Table 101. T1CON MMR Bit Descriptions Bit Value Description Reserved. 17 Event select bit. This bit is set by the user to enable time capture of an event. This bit is cleared by the user to ...
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T2LD Register Name: T2LD Address: 0xFFFF0360 Default 0x0000 value: Access: Read/write T2LD is a 16-bit register load register. T2VAL Register Name: T2VAL Address: 0xFFFF0364 Default 0xFFFF value: Access: Read T2VAL is a 16-bit read-only register that represents the current state ...
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ADuC7023 Secure Clear Bit (Watchdog Mode Only) The secure clear bit is provided for a higher level of protection. When set, a specific sequential value must be written to T2CLRI to avoid a watchdog reset. The value is a sequence ...
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HARDWARE DESIGN CONSIDERATIONS POWER SUPPLIES The ADuC7023 operational power supply voltage range is 2 3.6 V. Separate analog and digital power supply pins (AV and IOV , respectively) allow kept relatively free ...
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ADuC7023 GROUNDING AND BOARD LAYOUT RECOMMENDATIONS As with all high resolution data converters, special attention must be paid to grounding and PC board layout of the ADuC7023-based designs to achieve optimum performance from the ADCs and DACs. Although the parts ...
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POWER-ON RESET OPERATION An internal power-on reset (POR) is implemented on the ADuC7023. For LV below 2.40 V typical, the internal POR DD holds the part in reset rises above 2. internal DD timer times out ...
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ADuC7023 TYPICAL SYSTEM CONFIGURATION A typical ADuC7023 configuration is shown in Figure 54. It summarizes some of the hardware considerations. The bottom of the LFCSP package has an exposed pad that needs to be soldered to a metal plate on ...
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... These systems consist of the following PC-based (Windows® compatible) hardware and software development tools. Hardware The hardware sytsem uses the ADuC7023 evaluation board, aserial port programming cable, and a RDI-compliant JTAG emulator (included in the ADuC7023 QuickStart Plus only). Software The software system has an integrated development environment, incorporating an assembler, compiler, and nonintrusive JTAG-based debugger ...
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ADuC7023 OUTLINE DIMENSIONS PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE PIN 1 INDICATOR 0.80 0.75 0.70 SEATING PLANE 6.10 0.30 6.00 SQ 0.23 5.90 0. 0.50 BSC 21 20 0.45 TOP VIEW BOTTOM VIEW 0.40 0.35 0.05 ...
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... ORDERING GUIDE ADC DAC 1 Model Channels Channels ADuC7023BCP6Z62I 12 4 ADuC7023BCP6Z62IRL 12 4 ADuC7023BCP6Z62IR7 12 4 ADuC7023BCPZ62I 12 4 ADuC7023BCPZ62I- ADuC7023BCPZ62I- EVAL-ADuC7023QSPZ EVAL-ADuC7023QSPZ1 RoHS Compliant Part. FLASH/ Temperature RAM GPIO Downloader Range −40°C to +125° kB −40°C to +125° kB −40°C to +125°C ...
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ADuC7023 NOTES Rev Page ...
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NOTES Rev Page ADuC7023 ...
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ADuC7023 NOTES refers to a communications protocol originally developed by Philips Semiconductors (now NXP Semiconductors). ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08675-0-7/10(B) Rev ...