EVAL-ADUC7023QSPZ1 Analog Devices Inc, EVAL-ADUC7023QSPZ1 Datasheet - Page 11

• Manufacturer Part Number: EVAL-ADUC7023QSPZ1
• Description: BOARD EVAL FOR ADUC7023
• Manufacturer: Analog Devices Inc

Specifications of EVAL-ADUC7023QSPZ1

• Silicon Manufacturer: Analog Devices
• Core Architecture: ARM
• Core Sub-architecture: ARM7TDMI
• Silicon Core Number: ADuC7023
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 6. SPI Slave Mode Timing (Phase Mode = 1)
Parameter
t
t
t
t
t
t
t
t
t
t
t
1
SS
SL
SH
DAV
DSU
DHD
DF
DR
SR
SF
SFS
t
UCLK
= 23.9 ns. It corresponds to the 41.78 MHz internal clock from the PLL before the clock divider.
(POLARITY = 1)
(POLARITY = 0)
Description
SS to SCLK edge
SCLK low pulse width
SCLK high pulse width
Data output valid after SCLK edge
Data input setup time before SCLK edge
Data input hold time after SCLK edge
Data output fall time
Data output rise time
SCLK rise time
SCLK fall time
SS high after SCLK edge
SCLK
SCLK
MOSI
MISO
SS
t
SS
1
1
t
t
DAV
DSU
t
SH
Figure 5. SPI Slave Mode Timing (Phase Mode = 1)
MSB IN
1
t
DHD
1
MSB
t
SL
Rev. B | Page 11 of 96
t
DF
t
BIT 6 TO BIT 1
DR
BIT 6 TO BIT 1
Min
200
1 × t
2 × t
0
UCLK
UCLK
t
SR
Typ
(SPIDIV + 1) × t
(SPIDIV + 1) × t
5
5
5
5
LSB IN
t
SF
LSB
t
SFS
UCLK
UCLK
Max
25
12.5
12.5
12.5
12.5
ADuC7023
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns