EA-OEM-315 Embedded Artists, EA-OEM-315 Datasheet - Page 7

• Manufacturer Part Number: EA-OEM-315
• Description: KIT LPC3141 SODIMM 66X48 200POS
• Manufacturer: Embedded Artists
• Type: MCUr

Specifications of EA-OEM-315

• Contents: Board
• For Use With/related Products: LPC3141
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
Table 4.
Pin names with prefix m are multiplexed pins. See
LPC3141_3143
Preliminary data sheet
Pin name
USB_DM
USB_VDDA12_PLL
USB_VDDA33_DRV
USB_VDDA33
USB_VSSA_TERM
USB_GNDA
USB_VSSA_REF
JTAG
JTAGSEL
TDI
TRST_N
TCK
TMS
SCAN_TDO
ARM_TDO
BUF_TRST_N
BUF_TCK
BUF_TMS
UART
mUART_CTS_N
mUART_RTS_N
UART_RXD
UART_TXD
I
I2C_SDA0
I2C_SCL0
I2C_SDA1
I2C_SCL1
2
C-bus master/slave interface
[4]
[4]
Pin description
[4]
[4]
[4][5]
[4][5]
BGA
Ball
N2
L1
M2
P1
L3
N1
K4
N11
K9
P13
M14
P10
F10
E11
F11
D13
D14
N13
P14
P12
N12
C10
D10
E12
E13
…continued
Digital
I/O
level
[1]
SUP3
SUP1
SUP3
SUP3
-
-
-
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
SUP3
All information provided in this document is subject to legal disclaimers.
DI
Application
function
AIO
Supply
Supply
Supply
Ground
Ground
Ground
DI
DI
DI
DI
DO
DO
DO
DO
DO
DI/GPIO
DO/GPIO
DI/GPIO
DO/GPIO
DIO
DIO
DIO
DIO
Rev. 0.16 — 27 May 2010
Table 10
Pin
state
after
reset
-
-
-
-
-
-
-
I:PD
I:PU
I:PD
I:PD
I:PU
O/Z
O
O
O
O
I
O
I
O
I
I
O
O
for pin function selection of multiplexed pins.
[2]
Cell type
[3]
AIO1
PS3
PS3
PS3
CG1
CG1
CG1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
DIO1
IICD
IICC
DIO1
DIO1
Description
USB D− connection with integrated 45 Ω
termination resistor.
USB PLL supply.
USB analog supply for driver.
USB analog supply for PHY.
USB analog ground for clean reference for
on chip termination resistors.
USB analog ground.
USB analog ground for clean reference.
JTAG selection. Controls output function of
SCAN_TDO and ARM_TDO signals. Must
be LOW during power-on reset.
JTAG data input.
JTAG TAP Controller Reset Input. Must be
LOW during power-on reset.
JTAG clock input.
JTAG mode select input.
JTAG TDO signal from scan TAP controller.
Pin state is controlled by JTAGSEL.
JTAG TPO signal from ARM926 TAP
controller.
Buffered TRST_N out signal. Used for
connecting an on board TAP controller
(FPGA, DSP, etc.).
Buffered TCK out signal. Used for connecting
an on board TAP controller (FPGA, DSP,
etc.).
Buffered TMS out signal. Used for
connecting an on board TAP controller
(FPGA, DSP, etc.).
UART clear to send (active LOW).
UART ready to send (active LOW).
UART serial input.
UART serial output.
I
I
I
I
2
2
2
2
C0-bus serial data line.
C0-bus serial clock line.
C1-bus serial data line.
C1-bus serial clock line.
LPC3141/3143
© NXP B.V. 2010. All rights reserved.
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