EA-OEM-509 Embedded Artists, EA-OEM-509 Datasheet
EA-OEM-509
Specifications of EA-OEM-509
Related parts for EA-OEM-509
EA-OEM-509 Summary of contents
Page 1
... C-bus interfaces, one eight-channel, 12-bit ADC, a 10-bit DAC, a Quadrature Encoder Interface, four general purpose timers, two general purpose PWMs with six outputs each and one motor control PWM, an ultra-low power RTC with separate battery supply and event recorder, a windowed watchdog timer, a CRC calculation engine 165 general purpose I/O pins, and more ...
Page 2
... Cortex-M3 system tick timer, including an external clock input option. Standard JTAG test/debug interface as well as Serial Wire Debug and Serial WireTrace Port options. Emulation trace module supports real-time trace. Boundary scan for simplified board testing. Non-maskable Interrupt (NMI) input. ...
Page 3
... One motor control PWM with support for three-phase motor control. Real-Time Clock (RTC) with a separate power domain. The RTC is clocked by a dedicated RTC oscillator. The RTC block includes 20 bytes of battery-powered backup registers, allowing system status to be stored when the rest of the chip is powered off ...
Page 4
... A second, dedicated PLL may be used for USB interface in order to allow added flexibility for the Main PLL settings. Versatile pin function selection feature allows many possibilities for using on-chip peripheral functions. Unique device serial number for identification purposes. Single 3.3 V power supply (2 3.6 V). Temperature range of 40 C. ...
Page 5
... LPC1778FBD144 LQFP144 LPC1777 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm LPC1777FBD208 LQFP208 LPC1776 plastic low profile quad flat package; 208 leads; body 28 28 1.4 mm ...
Page 6
NXP Semiconductors Table 2. LPC178x/7x ordering options All parts include two CAN channels, three SSP interfaces, three I 12-bit ADC. Type number Flash CPU (kB) SRAM (kB) LPC178x LPC1788FBD208/ 512 64 LPC1788FET208 LPC1788FET180 512 64 LPC1788FBD144 512 64 LPC1787FBD208 512 ...
Page 7
NXP Semiconductors 5. Block diagram debug JTAG port interface TEST/DEBUG INTERFACE CORTEX-M3 I-code bus slave EMC slave (1) LCD slave HIGH-SPEED GPIO APB slave group 0 UART0/1 I CAN 0/1 TIMER 0/1 WINDOWED WDT PWM0/1 12-bit ADC PIN CONNECT GPIO ...
Page 8
... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration (LQFP208) Fig 3. Pin configuration (TFBGA208) LPC178X_7X Objective data sheet 1 LPC178x/7xFBD208 52 ball A1 index area LPC178x/ Transparent top view All information provided in this document is subject to legal disclaimers. Rev. 2 — 27 May 2011 LPC178x/7x 32-bit ARM Cortex-M3 microcontroller ...
Page 9
... ADC positive reference pin (VREFP). All port pins Pn[m] are multiplexed, and the functions appear in their order defined in the FUNC bits of the corresponding IOCON register. Each port pin can support up to eight multiplexed functions. IOCON register FUNC values which are reserved are noted as “ ...
Page 10
... Table 2 (Ethernet, USB, LCD, QEI, SD/MMC, DAC pins) and Description I/O Port 0: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 0 pins depends upon the pin function selected via the pin connect block. [3] I; I/O P0[0] — General purpose digital input/output pin. ...
Page 11
... LCD_VD[1] — LCD data. [3] I; I/O P0[6] — General purpose digital input/output pin I/O I2S_RX_SDA — I and read by the receiver. Corresponds to the signal SD in the 2 I S-bus specification. I/O SSP1_SSEL1 — Slave Select for SSP1. O T2_MAT0 — Match output for Timer 2, channel 0. O U1_RTS — ...
Page 12
... LCD_VD[16] — LCD data. [ I/O P0[9] — General purpose digital input/output pin. 2 I/O I2S_TX_SDA — I and read by the receiver. Corresponds to the signal SD in the 2 I S-bus specification. I/O SSP1_MOSI — Master Out Slave In for SSP1. O T2_MAT3 — Match output for Timer 2, channel 3. ...
Page 13
... I; I/O P0[17] — General purpose digital input/output pin U1_CTS — Clear to Send input for UART1. I/O SSP0_MISO — Master In Slave Out for SSP0. All information provided in this document is subject to legal disclaimers. Rev. 2 — 27 May 2011 LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 7 © ...
Page 14
... LCD_VD[13] — LCD data. [3] I; I/O P0[20] — General purpose digital input/output pin U1_DTR — Data Terminal Ready output for UART1. Can also be configured RS-485/EIA-485 output enable signal for UART1. I/O SD_CMD — Command line for SD card interface. 2 I/O I2C1_SCL — clock input/output (this pin does not use a specialized I2C pad) ...
Page 15
... I ADC0_IN[2] — A/D converter 0, input 2. When configured as an ADC input, the digital function of the pin must be disabled. I/O I2S_RX_SDA — Receive data driven by the transmitter and read by the receiver. Corresponds to the signal SD in the 2 I S-bus specification. O U3_TXD — Transmitter output for UART3. ...
Page 16
... I/O USB_D+2 — USB port 2 bidirectional D+ line. I/O Port 1: Port bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block [3] I; I/O P1[0] — General purpose digital input/output pin. ...
Page 17
NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[4] 192 A5 C6 133 P1[5] 156 A17 B13 - P1[6] 171 B11 B10 - P1[7] 153 D14 C13 - P1[8] 190 ...
Page 18
NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[11] 163 A14 A12 - P1[12] 157 A16 A14 - P1[13] 147 D16 D14 - P1[14] 184 A7 D8 128 P1[15] 182 ...
Page 19
NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[19 P1[20 P1[21 P1[22 LPC178X_7X Objective ...
Page 20
NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[23 P1[24 P1[25] 80 T10 L7 56 P1[26] 82 R10 P8 57 LPC178X_7X Objective ...
Page 21
NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P1[27] 88 T12 M9 61 P1[28] 90 T13 P10 63 P1[29] 92 U14 N10 64 P1[30 LPC178X_7X Objective ...
Page 22
... I2C0_SCL — clock input/output (this pin does not use a specialized I2C pad. I/O Port 2: Port bit I/O port with individual direction controls for each bit. The operation of port 1 pins depends upon the pin function selected via the pin connect block. [3] I; I/O P2[0] — ...
Page 23
... I/O P2[5] — General purpose digital input/output pin PWM1[6] — Pulse Width Modulator 1, channel 6 output. O U1_DTR — Data Terminal Ready output for UART1. Can also be configured RS-485/EIA-485 output enable signal for UART1. O T2_MAT0 — Match output for Timer 2, channel — Function reserved. ...
Page 24
... I/O P2[8] — General purpose digital input/output pin CAN_TD2 — CAN2 transmitter output. O U2_TXD — Transmitter output for UART2. I U1_CTS — Clear to Send input for UART1. O ENET_MDC — Ethernet MIIM clock — Function reserved. O LCD_VD[2] — LCD data. O LCD_VD[6] — LCD data. ...
Page 25
... I EINT3 — External interrupt 3 input. I/O SD_DAT[3] — Data line 3 for SD card interface. I/O I2S_TX_SDA — Transmit data driven by the transmitter and read by the receiver. Corresponds to the signal SD in the 2 I S-bus specification — Function reserved. O LCD_VD[5] — LCD data. ...
Page 26
NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P2[15] 99 P13 - - P2[16] 87 R11 P9 - P2[17] 95 R13 P11 - P2[18 P2[19] 67 ...
Page 27
... I2C pad). O T3_MAT3 — Match output for Timer 3, channel 3. I/O Port 3: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 3 pins depends upon the pin function selected via the pin connect block. [3] I; I/O P3[0] — General purpose digital input/output pin. ...
Page 28
... PU I/O EMC_D[18] — External memory data line 18. O PWM0[3] — Pulse Width Modulator 0, output 3. I U1_CTS — Clear to Send input for UART1. All information provided in this document is subject to legal disclaimers. Rev. 2 — 27 May 2011 LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Table 7 © NXP B.V. 2011. All rights reserved. ...
Page 29
... PU I/O EMC_D[21] — External memory data line 21. O PWM0[6] — Pulse Width Modulator 0, output 6. O U1_DTR — Data Terminal Ready output for UART1. Can also be configured RS-485/EIA-485 output enable signal for UART1. [3] I; I/O P3[22] — General purpose digital input/output pin. ...
Page 30
... R — Function reserved. O T1_MAT2 — Match output for Timer 1, channel 2. I/O Port 4: Port 32-bit I/O port with individual direction controls for each bit. The operation of port 4 pins depends upon the pin function selected via the pin connect block. [3] I; I/O P4[0] — General purpose digital input/output pin. ...
Page 31
NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P4[6] 113 M14 K10 78 P4[7] 121 L16 K12 84 P4[8]/ 127 J17 J11 88 P4[9] 131 H17 H12 91 P4[10] 135 ...
Page 32
NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol P4[21] 115 M15 - - P4[22] 123 K14 - - P4[23] 129 J15 - - P4[24] 183 B8 C8 127 P4[25] 179 ...
Page 33
... PU O EMC_CS1 — LOW active Chip Select 1 signal. I/O Port 5: Port 5-bit I/O port with individual direction controls for each bit. The operation of port 5 pins depends upon the pin function selected via the pin connect block. [3] I; I/O P5[0] — General purpose digital input/output pin. ...
Page 34
... O Reset status output. A LOW output on this pin indicates that the device is in the reset state, for any reason. This reflects the RESET input pin and all internal reset sources. [13] O RTC_ALARM — RTC controlled output. This is a 1.8 V pin. It goes HIGH when a RTC alarm is generated ...
Page 35
NXP Semiconductors Table 3. Pin description …continued Not all functions are available on all parts. See pins). Symbol V 26, H4, G1, 18, DD(REG)(3V3) 86, P11, N9, 60, 174 D11 E9 121 DDA V 15, ...
Page 36
NXP Semiconductors [ Input Output Ground Supply. [ tolerant pad providing digital I/O functions with TTL levels and hysteresis. [4] <tbd> [ tolerant pad providing digital I/O functions ...
Page 37
NXP Semiconductors Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Ball Symbol Ball Symbol 9 P1[ P0[ P2[4] Row E 1 P0[26 ...
Page 38
NXP Semiconductors Table 4. Pin allocation table TFBGA208 Not all functions are available on all parts. See Ball Symbol Ball Symbol P0[19] Row M 1 P3[15 ...
Page 39
NXP Semiconductors Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Ball Symbol Ball Symbol Row A 5 P1[ P1[ P0[9] 14 Row B 1 JTAG_TDO_SWO 2 5 P1[0] 6 ...
Page 40
NXP Semiconductors Table 5. Pin allocation table TFBGA180 Not all functions are available on all parts. See Ball Symbol Ball Symbol Row J 1 RESET 2 5 P0[13 P0[18] 14 Row K 1 VBAT 2 ...
Page 41
... The LPC178x/7x contain a total on-chip static RAM data memory. This includes the main 64 kB SRAM, accessible by the CPU and DMA controller on a higher-speed bus, and up to two additional 16 kB each SRAM blocks situated on a separate slave port on the AHB multilayer matrix. ...
Page 42
... Figure 6 program viewpoint following reset. The interrupt vector area supports address remapping. The AHB peripheral area size, and is divided to allow for up to 128 peripherals. The APB peripheral area size and is divided to allow for peripherals. Each peripheral of either type is allocated space. This allows simplifying the address decoding for each peripheral ...
Page 43
APB1 peripherals 0x4010 0000 31 system control 0x400F C000 reserved (1) 16 SD/MMC 0x400C 0000 (1) 15 QEI 0x400B C000 14 motor control PWM 0x400B 8000 reserved 13 0x400B ...
Page 44
... Software interrupt generation. 7.8.2 Interrupt sources Each peripheral device has one interrupt line connected to the NVIC but may have several interrupt flags. Individual interrupt flags may also represent more than one interrupt source. Any pin on port 0 and port 2 regardless of the selected function can be programmed to generate an interrupt on a rising edge, a falling edge, or both ...
Page 45
NXP Semiconductors Table 7. External memory controller pin configuration Part Data bus pins Address bus LPC1788FBD208 EMC_D[31:0] LPC1788FET208 EMC_D[31:0] LPC1788FET180 EMC_D[15:0] LPC1788FBD144 EMC_D[7:0] LPC1787FBD208 EMC_D[31:0] LPC1786FBD208 EMC_D[31:0] LPC1785FBD208 EMC_D[31:0] LPC1778FBD208 EMC_D[31:0] LPC1778FET208 EMC_D[31:0] LPC1778FET180 EMC_D[15:0] LPC1778FBD144 EMC_D[7:0] LPC1777FBD208 EMC_D[31:0] LPC1776FBD208 ...
Page 46
... The GPDMA enables peripheral-to-memory, memory-to-peripheral, peripheral-to-peripheral, and memory-to-memory transactions. The source and destination areas can each be either a memory region or a peripheral and can be accessed through the AHB master. The GPDMA controller allows data transfers between the various on-chip SRAM areas and supports the SD/MMC card interface, all SSPs, the ...
Page 47
... An interrupt to the processor can be generated on a DMA completion or when a DMA error has occurred. • Raw interrupt status. The DMA error and DMA count raw interrupt status can be read prior to masking. 7.12 CRC engine The Cyclic Redundancy Check (CRC) generator with programmable polynomial settings supports several CRC standards commonly used ...
Page 48
... CPU and other system functions. A built-in FIFO acts as a buffer for display data, providing flexibility for system timing. Hardware cursor support can further reduce the amount of CPU time needed to operate the display. 7.13.1 Features • AHB master interface to access frame buffer. ...
Page 49
... Ethernet Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76. The Ethernet block contains a full featured 10 Mbit/s or 100 Mbit/s Ethernet MAC designed to provide optimized performance through the use of DMA hardware acceleration. Features include a generous suite of control registers, half or full duplex operation, flow control, control frames, hardware acceleration for transmit retry, receive packet filtering and wake-up on LAN activity ...
Page 50
... The device controller enables 12 Mbit/s data exchange with a USB host controller. It consists of a register interface, serial interface engine, endpoint buffer memory, and a DMA controller. The serial interface engine decodes the USB data stream and writes data to the appropriate endpoint buffer. The status of a completed USB transfer or error condition is indicated via status registers ...
Page 51
... Device pins that are not connected to a specific peripheral function are controlled by the GPIO registers. Pins may be dynamically configured as inputs or outputs. Separate registers allow setting or clearing any number of outputs simultaneously. The value of the output register may be read back as well as the current state of the port pins. LPC178x/7x use accelerated GPIO functions: LPC178X_7X Objective data sheet All information provided in this document is subject to legal disclaimers ...
Page 52
... Power-down mode. Each enabled interrupt can be used to wake up the chip from Power-down mode. 7.17.1 Features • Bit level set and clear registers allow a single instruction to set or clear any number of bits in one port. • Direction control of individual bits. ...
Page 53
... RS-485/9-bit mode allowing both software address detection and automatic address detection using 9-bit mode. The UARTs include a fractional baud rate generator. Standard baud rates such as 115200 Bd can be achieved with any crystal frequency above 2 MHz. 7.20.1 Features • Maximum UART data bit rate of 7.5 MBit/s. • ...
Page 54
... The I C-bus is bidirectional for inter-IC control using only two wires: a Serial Clock Line (SCL) and a Serial Data Line (SDA). Each device is recognized by a unique address and can operate as either a receiver-only device (e.g., an LCD driver transmitter with the capability to both receive and send information (such as memory). Transmitters and/or receivers can operate in either master or slave mode, depending on whether the chip has to initiate a data transfer or is only addressed ...
Page 55
... S-bus specification defines a 3-wire serial bus using one data line, one clock line, and one word select signal. The basic I master, and one slave. The I and receive channel, each of which can operate as either a master or a slave. 7.23.1 Features • The interface has separate input/output channels each of which can operate in master or slave mode. • ...
Page 56
... Pulse Width Modulator (PWM) The LPC178x/7x contain two PWMs. The PWM is based on the standard Timer block and inherits all of its features, although only the PWM function is pinned out on the LPC178x/7x. The Timer is designed to count cycles of the system derived clock and optionally switch pins, generate interrupts or perform other actions when specified timer values occur, based on seven match registers ...
Page 57
... Again, the PWMMR0 match register controls the PWM cycle rate. The other match registers control the two PWM edge positions. Additional double edge controlled PWM outputs require only two match registers each, since the repetition rate is the same for all PWM outputs. ...
Page 58
... NXP Semiconductors PWM to immediately release all motor drive outputs. At the same time, the motor control PWM is highly configurable for other generalized timing, counting, capture, and compare applications. The maximum PWM speed is determined by the PWM resolution (n) and the operating frequency f: PWM speed = f/2 Table 8 ...
Page 59
... RTC and backup registers The RTC is a set of counters for measuring time when system power is on, and optionally when it is off. The RTC on the LPC178x/7x is designed to have extremely low power consumption, i.e. less than 1 A. The RTC will typically run from the main chip power supply, conserving battery power while the rest of the device is powered up ...
Page 60
... An event is defined as a level change at the digital event inputs. • For each event channel, two timestamps mark the first and the last occurrence of an event. Each channel also has a dedicated counter tracking the total number of events. Timestamp values are taken from the RTC. ...
Page 61
... PLL. The clock selected as the PLL input is PLLCLKIN. The ARM processor clock frequency is referred to as CCLK elsewhere in this document. The frequencies of PLLCLKIN and CCLK are the same value unless the PLL is active and connected. The clock frequency for each peripheral can be selected individually and is referred to as PCLK. Refer to LPC178X_7X ...
Page 62
... Main PLL is used, then its output frequency must be an integer multiple of all other clocks needed in the system. PLL1 takes its input only from the main oscillator, requiring an external crystal in the range MHz. In each PLL, the Current Controlled Oscillator (CCO) operates in the range of 156 MHz to 320 MHz, so there are additional dividers to bring the output down to the desired frequencies ...
Page 63
... MHz IRC oscillator as the clock source. This allows chip operation to resume quickly. If the main oscillator or the PLL is needed by the application, software will need to enable these features and wait for them to stabilize before they are used as a clock source. ...
Page 64
... IRC 60 s to start-up. After this 4 IRC cycles will expire before the code execution can then be resumed if the code was running from SRAM. In the meantime, the flash wake-up timer then counts 12 MHz IRC clock cycles to make the 100 s flash start-up time ...
Page 65
... The WIC eliminates the need to periodically wake up the CPU and poll the interrupts resulting in additional power savings. 7.33.5 Peripheral power control A power control for peripherals feature allows individual peripherals to be turned off if they are not needed in the application, resulting in additional power savings. 7.33.6 Power domains ...
Page 66
... ARM Cortex-M3 microcontroller DD(3V3) ). Having the on-chip voltage regulator is present. Therefore, DD(REG)(3V3) is available. DD(REG)(3V3) to core to memories, peripherals, oscillators, PLLs ULTRA-LOW POWER REGULATOR BACKUP REGISTERS REAL-TIME CLOCK DAC ADC 002aaf530 © NXP B.V. 2011. All rights reserved. ) and 66 of 117 ...
Page 67
... V, the BOD asserts an interrupt signal to the Vectored Interrupt Controller. This signal can be enabled for interrupt in the Interrupt Enable Register in the NVIC in order to cause a CPU interrupt; if not, software can monitor the signal by reading a dedicated status register. The second stage of low-voltage detection asserts reset to inactivate the LPC178x/7x ...
Page 68
... Emulation and debugging Debug and trace functions are integrated into the ARM Cortex-M3. Serial wire debug and trace functions are supported in addition to a standard JTAG debug and parallel trace functions. The ARM Cortex-M3 is configured to support up to eight breakpoints and four watch points. LPC178X_7X Objective data sheet All information provided in this document is subject to legal disclaimers ...
Page 69
... The following applies to the limiting values: a) This product includes circuitry specifically designed for the protection of its internal devices from the damaging effects of excessive static charge. Nonetheless suggested that conventional precautions be taken to avoid applying greater than the rated maximum. b) Parameters are valid over operating temperature range unless otherwise specified. All voltages are with respect to V otherwise noted ...
Page 70
NXP Semiconductors 9. Thermal characteristics 9.1 Thermal characteristics The average chip junction temperature, T equation amb • ambient temperature (C), amb • R th(j-a) • sum of internal and I/O power dissipation ...
Page 71
NXP Semiconductors 10. Static characteristics Table 11. Static characteristics +85 C, unless otherwise specified. amb Symbol Parameter Supply pins V supply voltage (3.3 V) DD(3V3) V regulator supply voltage DD(REG)(3V3) (3.3 V) ...
Page 72
NXP Semiconductors Table 11. Static characteristics …continued +85 C, unless otherwise specified. amb Symbol Parameter I ADC supply current DD(ADC) I ADC input current I(ADC) Standard port pins, RESET I LOW-level input ...
Page 73
... Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply voltages. [1] For USB operation 3.0 V V [2] DD((3V3) [3] The RTC typically fails when V i(VBAT C for all power consumption measurements DD(REG)(3V3) amb [5] IRC running at 12 MHz; main oscillator and PLL disabled; PCLK = CCLK/4. ...
Page 74
NXP Semiconductors [9] All internal pull-ups disabled. All pins configured as output and driven LOW C. [10 3 DDA amb = 25 C. [11 3 i(VREFP) amb [12] Including ...
Page 75
NXP Semiconductors X (X) Conditions: V Fig 10. Power-down mode: Regulator supply current I X (X) Conditions: V Fig 11. Deep power-down mode: Battery supply current I LPC178X_7X Objective data sheet <tbd> ...
Page 76
... The supply current per peripheral is measured as the difference in supply current between the peripheral block enabled and the peripheral block disabled in the PCONP register. All other blocks are disabled and no code is executed. Measured on a typical sample C. The peripheral clock was set to PCLK = CCLK/4 with CCLK = 12 MHz, ...
Page 77
NXP Semiconductors Table 12. amb Peripheral EMC RTC USB + PLL1 Ethernet LPC178X_7X Objective data sheet Power consumption for individual analog and digital blocks <tbd> V. PCLK = CCLK/4. DD(REG)(3V3) Conditions PCENET bit ...
Page 78
NXP Semiconductors 10.3 Electrical pin characteristics 3 (V) 3.2 2.8 2.4 Conditions: V Fig 12. Typical HIGH-level output voltage (mA) 10 Conditions: V Fig 13. Typical LOW-level output current I LPC178X_7X Objective data ...
Page 79
NXP Semiconductors I (μA) Conditions: V Fig 14. Typical pull-up current (μ −10 Conditions: V Fig 15. Typical pull-down current I LPC178X_7X Objective data sheet +10 pu −10 − ...
Page 80
... LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Min Typ Max [1] 10000 100000 - 100 105 [2] 0.95 1 1.05 Min Typ Max 200 375 400 100000 500000 - © NXP B.V. 2011. All rights reserved. Unit cycles years years ms ms Unit kHz cycles years years 80 of 117 ...
Page 81
... pF amb [1] Symbol Parameter T clock cycle time cy(clk) [2] Read cycle parameters t CS LOW to address valid CSLAV time t CS LOW to OE LOW time CSLOEL t CS LOW to BLS LOW time CSLBLSL t OE LOW to OE HIGH time OELOEH t memory access time am t data input hold time ...
Page 82
... BLSHDNV time [1] Parameters are shown [2] Parameters specified for DD(IO) [3] Latest of address valid, CS LOW, OE LOW, BS LOW (PB = 1). [4] After End Of Read (EOR): Earliest of CS HIGH, OE HIGH, BLSx HIGH (PB = 1), address invalid. [5] End Of Write (EOW): Earliest of address invalid, CS HIGH, BLSx HIGH ( BLSx WE D Fig 16. External static memory read/write access ( ...
Page 83
... OE RD BLSx WE D Fig 17. External static memory read/write access (PB = BLSx Fig 18. External static memory burst read cycle Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits pF amb Values guaranteed by design. Symbol Parameter Common to read and write cycles ...
Page 84
... NXP Semiconductors Table 16. Dynamic characteristics: Dynamic external memory interface, read strategy bits (RD bits pF amb Values guaranteed by design. Symbol Parameter t write hold time h(W) t output enable valid delay time d(GV) t output enable hold time h(G) t address valid delay time ...
Page 85
... The programmable delay blocks are controlled by the EMCDLYCTL register in the EMC register block. All delay times are incremental delays for each element starting from delay block 0. See the LPC178x/7x user manual for details. LPC178X_7X Objective data sheet t h(CS) ...
Page 86
... CLCH t CHCL [1] Parameters are valid over operating temperature range unless otherwise specified. Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply [2] voltages. Fig 20. External clock timing (with an amplitude of at least V 11.4 Internal oscillators Table 20. amb ...
Page 87
NXP Semiconductors X (X) Conditions: Frequency values are typical values. 12 MHz accuracy is guaranteed for 2.7 V fall outside the 12 MHz accuracy specification for voltages below 2.7 V. Fig ...
Page 88
NXP Semiconductors Table 22. amb Symbol T cy(clk v(Q) t h(Q) = (SSPCLKDIV SCR) CPSDVSR [1] T cy(clk function of the main ...
Page 89
NXP Semiconductors SCK (CPOL = 0) SCK (CPOL = 1) Fig 23. SSP slave timing in SPI mode 2 11.7 I C-bus Table 23. amb Symbol f SCL LOW t HIGH LPC178X_7X Objective ...
Page 90
... SCL; applies to data in transmission HD;DAT and the acknowledge. [4] A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the V (min) of the SCL signal) to bridge the undefined region of the falling edge of SCL. IH ...
Page 91
NXP Semiconductors 2 11.8 I S-bus interface Table 24. amb Symbol common to input and output output t v(Q) input t su(D) t h(D) [1] CCLK = 100 ...
Page 92
NXP Semiconductors I2S_RX_SCK I2S_RX_SDA I2S_RX_WS Fig 26. I 11.9 USB Table 25. Dynamic characteristics of USB pins (full-speed) pF 1 Symbol Parameter t rise time r t ...
Page 93
NXP Semiconductors t PERIOD crossover point differential data lines differential data to n × t Fig 27. Differential data-to-EOP transition skew and EOP width 11.10 Ethernet Remark: The Ethernet block is available on parts LPC1788/86 and LPC1778/76. Table 26. ...
Page 94
NXP Semiconductors Fig 28. Ethernet timing 11.11 LCD Remark: The LCD controller is available on parts LPC1788/87/86/85. Table 27. Values listed describe design constraints. Symbol T cy(clk) X (X) Fig 29. LCD timing 11.12 SD/MMC Remark: The SD/MMC card interface ...
Page 95
... Conditions analog input voltage analog input capacitance voltage source interface resistance differential linearity error integral non-linearity offset error gain error absolute error ADC clock frequency All information provided in this document is subject to legal disclaimers. Rev. 2 — 27 May 2011 LPC178x/7x 32-bit ARM Cortex-M3 microcontroller ...
Page 96
... The offset error (E straight line which fits the ideal curve. See [6] The gain error (E curve after removing offset error, and the straight line which fits the ideal transfer curve. See [7] The absolute error (E curve of the non-calibrated ADC and the ideal transfer curve. See ...
Page 97
... E O (1) Example of an actual transfer curve. (2) The ideal transfer curve. (3) Differential linearity error ( (4) Integral non-linearity (E ). L(adj) (5) Center of a step of the actual transfer curve. Fig 31. 12-bit ADC characteristics LPC178X_7X Objective data sheet (2) (5) (4) (3) 1 LSB (ideal) 4090 4 5 ...
Page 98
... C to +85 C unless otherwise specified amb Parameter Conditions differential linearity error integral non-linearity offset error gain error load capacitance load resistance All information provided in this document is subject to legal disclaimers. Rev. 2 — 27 May 2011 LPC178x/7x 32-bit ARM Cortex-M3 microcontroller R i2 100 Ω - 600 Ω ...
Page 99
NXP Semiconductors 14. Application information 14.1 Suggested USB interface solutions Remark: The USB controller is available as a device/Host/OTG controller on parts LPC1788/87/86/85 and LPC1778/77/76 and as device-only controller on parts LPC1774. LPC17xx Fig 33. USB interface on a self-powered ...
Page 100
NXP Semiconductors RSTOUT LPC17xx USB_SCL USB_SDA EINTn USB_D+ USB_D− USB_UP_LED Fig 35. USB OTG port configuration USB_UP_LED USB_D+ USB_D− LPC17xx USB_PWRD USB_OVRCR USB_PPWR Fig 36. USB host port configuration LPC178X_7X Objective data sheet V DD RESET_N ADR/PSW OE_N/INT_N V DD ...
Page 101
... C mode, a minimum of 200 mV(RMS) is needed. Fig 38. Slave mode operation of the on-chip oscillator In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF (Figure 38), with an amplitude between 200 mV(RMS) and 1000 mV(RMS). This corresponds to a square wave signal with a signal swing of between 280 mV and 1.4 V. ...
Page 102
NXP Semiconductors Fig 39. Oscillator modes and models: oscillation mode of operation and external crystal model used for C Table 32. Fundamental oscillation frequency F 1 MHz - 5 MHz 5 MHz - 10 MHz 10 MHz - 15 MHz ...
Page 103
... Digital input: Pull-down enabled/disabled • Digital input: Repeater mode enabled/disabled • Analog input The default configuration for standard I/O pins is input with pull-up enabled. The weak MOS devices provide a drive capability equivalent to pull-up and pull-down resistors. pin configured as digital output driver ...
Page 104
NXP Semiconductors 14.5 Reset pin configuration reset Fig 41. Reset pin configuration LPC178X_7X Objective data sheet GLITCH FILTER All information provided in this document is subject to legal disclaimers. Rev. 2 — 27 May ...
Page 105
... NXP Semiconductors 15. Package outline LQFP208; plastic low profile quad flat package; 208 leads; body 1 156 157 pin 1 index 208 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
Page 106
... NXP Semiconductors TFBGA208: plastic thin fine-pitch ball grid array package; 208 balls; body 0.7 mm ball A1 index area ball index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.4 0.8 0.5 15.1 mm 1.2 0.3 0.6 14.9 0.4 OUTLINE VERSION IEC SOT950-1 Fig 43. TFBGA208 package ...
Page 107
... NXP Semiconductors TFBGA180: thin fine-pitch ball grid array package; 180 balls; body 0.8 mm ball A1 index area ball A1 index area DIMENSIONS (mm are the original dimensions UNIT max. 0.35 0.85 0.5 12.2 mm 1.2 0.25 0.75 0.4 11.8 OUTLINE VERSION IEC SOT570-2 Fig 44. TFBGA180 package ...
Page 108
... NXP Semiconductors LQFP144: plastic low profile quad flat package; 144 leads; body 1 108 109 pin 1 index 144 DIMENSIONS (mm are the original dimensions) A UNIT max. 0.15 1.45 0.27 mm 1.6 0.25 0.05 1.35 0.17 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. ...
Page 109
... NXP Semiconductors 16. Soldering Footprint information for reflow soldering of LQFP208 package solder land occupied area DIMENSIONS 0.500 0.560 31.300 31.300 28.300 28.300 Fig 46. Reflow soldering of the LQFP208 package LPC178X_7X Objective data sheet Hx Gx (0.125 (8× Generic footprint pattern Refer to the package outline drawing for actual layout ...
Page 110
... NXP Semiconductors Footprint information for reflow soldering of TFBGA180 package P Hy solder land solder paste deposit solder land plus solder paste occupied area solder resist DIMENSIONS 0.80 0.400 0.400 0.550 12.575 12.575 Fig 47. Reflow soldering of the TFBGA180 package LPC178X_7X Objective data sheet ...
Page 111
... NXP Semiconductors Footprint information for reflow soldering of LQFP144 package solder land occupied area DIMENSIONS 0.500 0.560 23.300 23.300 20.300 20.300 Fig 48. Reflow soldering of the LQFP144 package LPC178X_7X Objective data sheet Hx Gx (0.125 (8× Generic footprint pattern Refer to the package outline drawing for actual layout ...
Page 112
... Direct Memory Access Digital Signal Processing End Of Packet Embedded Trace Macrocell General Purpose Input/Output Global Positioning System Heating, Venting, and Air Conditioning Internal RC Infrared Data Association Joint Test Action Group Media Access Control Media Independent Interface Management Open Host Controller Interface ...
Page 113
... NXP Semiconductors 18. Revision history Table 35. Revision history Document ID Release date LPC178X_7X v.2 20110527 • Modifications: Symbol names in • Reserved functions added in • Added function LCD_VD[5] to pin P0[10]. • Added function LCD_VD[10] to pin P0[11]. • Added function LCD_VD[13] to pin P0[19]. • Added function LCD_VD[14] to pin P0[20]. ...
Page 114
... NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer’s applications or products, or the application or use by customer’s third party customer(s). Customer is responsible for doing all necessary testing for the customer’ ...
Page 115
... NXP Semiconductors’ specifications such use shall be solely at customer’s 20. Contact information For more information, please visit: For sales office addresses, please send an email to: LPC178X_7X Objective data sheet own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
Page 116
... Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 7.15 USB interface . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.15.1 USB device controller . . . . . . . . . . . . . . . . . . . 50 7.15.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.15.2 USB host controller 7.15.2.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 7.15.3 USB OTG controller . . . . . . . . . . . . . . . . . . . . 51 7.15.3.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.16 SD/MMC card interface . . . . . . . . . . . . . . . . . 51 7.16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 7.17 Fast general purpose parallel I 7.17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.18 12-bit ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 7.19 10-bit DAC ...
Page 117
... Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116 LPC178x/7x 32-bit ARM Cortex-M3 microcontroller Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2011. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document identifier: LPC178X_7X All rights reserved ...