EA-OEM-315 Embedded Artists, EA-OEM-315 Datasheet - Page 21

• Manufacturer Part Number: EA-OEM-315
• Description: KIT LPC3141 SODIMM 66X48 200POS
• Manufacturer: Embedded Artists
• Type: MCUr

Specifications of EA-OEM-315

• Contents: Board
• For Use With/related Products: LPC3141
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
LPC3141_3143
Preliminary data sheet
6.12 Interrupt controller
6.13 Multi-layer AHB
Table 9:
[1]
The interrupt controller collects interrupt requests from multiple devices, masks interrupt
requests, and forwards the combined requests to the processor. The interrupt controller
also provides facilities to identify the interrupt requesting devices to be served.
This module has the following features:
The following blocks can generate interrupts:
The multi-layer AHB is an interconnection scheme based on the AHB protocol that
enables parallel access paths between multiple masters and slaves in a system.
Peripheral name
I
I
PCM interface
2
2
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
S0/1 receive
S0/1 transmit
AES decryption engine is available on LPC3143 only.
The interrupt controller decodes all the interrupt requests issued by the on-chip
peripherals.
Two interrupt lines (Fast Interrupt Request (FIQ), Interrupt Request (IRQ)) to the ARM
core. The ARM core supports two distinct levels of priority on all interrupt sources,
FIQ for high priority interrupts and IRQ for normal priority interrupts.
Software interrupt request capability associated with each request input.
Visibility of interrupts request state before masking.
Support for nesting of interrupt service routines.
Interrupts routed to IRQ and to FIQ are vectored.
Level interrupt support.
NAND flash controller
USB 2.0 HS OTG
Event router
10 bit ADC
UART
LCD interface
MCI
SPI
Timer 0, timer 1, timer 2, and timer 3
I
I
DMA
I
2
2
2
S transmit: I2STX_0 and I2STX_1
S receive: I2SRX_0 and I2SRX_1
C0-bus and I
Peripherals that support DMA
All information provided in this document is subject to legal disclaimers.
2
C1-bus controllers
Rev. 0.16 — 27 May 2010
Supported transfer types
Peripheral to Memory
Memory to peripheral
Memory to peripheral and peripheral to memory
LPC3141/3143
© NXP B.V. 2010. All rights reserved.
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