C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 33
![DEV KIT FOR F060/F062/F063](/photos/9/23/92355/c8051f060dk_sml.jpg)
C8051F060DK
Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F060-TB.pdf
(328 pages)
Specifications of C8051F060DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F060DK
Manufacturer:
Silicon Labs
Quantity:
135
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1.8.
The C8051F060/1/2/3/4/5/6/7 devices have two on-chip 16-bit SAR ADCs (ADC0 and ADC1), which can
be used independently in single-ended mode, or together in differential mode. ADC0 and ADC1 can
directly access on-chip or external RAM, using the DMA interface. With a maximum throughput of 1 Msps,
the ADCs offer 16 bit performance with two available linearity grades. ADC0 and ADC1 each have the
capability to use dedicated, on-chip voltage reference circuitry or an external voltage reference source.
The ADCs are under full control of the CIP-51 microcontroller via the associated Special Function Regis-
ters. The system controller can also put the ADCs into shutdown mode to save power.
Conversions can be started in four ways; a software command, an overflow of Timer 2, an overflow of
Timer 3, or an external signal input. This flexibility allows the start of conversion to be triggered by software
events, external HW signals, or a periodic timer overflow signal. The two ADCs can operate independently,
or be synchronized to perform conversions at the same time. Conversion completions are indicated by sta-
tus bits, and can generate interrupts. The resulting 16-bit data words are latched into SFRs upon comple-
tion of a conversion. A DMA interface is also provided, which can gather conversions from the ADCs, and
directly store them to on-chip or external RAM.
ADC0 also contains Window Compare registers, which can be configured to interrupt the controller when
ADC0 data is within or outside of a specified range. ADC0 can monitor a key voltage continuously in back-
ground mode, and not interrupt the controller unless the converted data is within the specified window.
16-Bit Analog to Digital Converters
(DC, -0.2 to 0.6 V)
(DC, -0.2 to 0.6 V)
AIN0G
AIN1G
AIN0
AIN1
Figure 1.12. 16-Bit ADC Block Diagram
Configuration and Control
ADC0
ADC1
16-Bit
16-Bit
Registers
SAR
SAR
Start Conversion
Rev. 1.2
Start Conversion
16
16
C8051F060/1/2/3/4/5/6/7
ADC Data
Registers
Write to AD1BUSY
Timer 3 Overflow
CNVSTR1
Timer 2 Overflow
Write to AD0BUSY
Write to AD0BUSY
Timer 3 Overflow
CNVSTR0
Timer 2 Overflow
Interface
Compare
Window
DMA
ADC0
Logic
33
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