C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 189
![DEV KIT FOR F060/F062/F063](/photos/9/23/92355/c8051f060dk_sml.jpg)
C8051F060DK
Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F060-TB.pdf
(328 pages)
Specifications of C8051F060DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F060DK
Manufacturer:
Silicon Labs
Quantity:
135
- Current page: 189 of 328
- Download datasheet (2Mb)
Bits7-0:
Bits7-6:
Bit5:
Bit4:
Bits3-2:
Bits1-0:
PGSEL7
R/W
R/W
Bit7
Bit7
-
PGSEL[7:0]: XRAM Page Select Bits.
The XRAM Page Select Bits provide the high byte of the 16-bit external data memory
address when using an 8-bit MOVX command, effectively selecting a 256-byte page of
RAM.
0x00: 0x0000 to 0x00FF
0x01: 0x0100 to 0x01FF
...
0xFE: 0xFE00 to 0xFEFF
0xFF: 0xFF00 to 0xFFFF
Unused. Read = 00b. Write = don’t care.
PRTSEL: EMIF Port Select.
0: EMIF not mapped to port pins.
1: EMIF active on P4-P7.
EMD2: EMIF Multiplex Mode Select.
0: EMIF operates in multiplexed address/data mode.
1: EMIF operates in non-multiplexed mode (separate address and data pins).
EMD1-0: EMIF Operating Mode Select.
These bits control the operating mode of the External Memory Interface.
00: Internal Only: MOVX accesses on-chip XRAM only. All effective addresses alias to on-chip
memory space.
01: Split Mode without Bank Select: Accesses below the 4 kB boundary are directed on-chip.
Accesses above the 4 kB boundary are directed off-chip. 8-bit off-chip MOVX operations use the
current contents of the Address High port latches to resolve upper address byte. Note that in
order to access off-chip space, EMI0CN must be set to a page that is not contained in the on-chip
address space.
10: Split Mode with Bank Select: Accesses below the 4 kB boundary are directed on-chip.
Accesses above the 4 kB boundary are directed off-chip. 8-bit off-chip MOVX operations use the
contents of EMI0CN to determine the high-byte of the address.
11: External Only: MOVX accesses off-chip XRAM only. On-chip XRAM is not visible to the CPU.
EALE1-0: ALE Pulse-Width Select Bits (only has effect when EMD2 = 0).
00: ALE high and ALE low pulse width = 1 SYSCLK cycle.
01: ALE high and ALE low pulse width = 2 SYSCLK cycles.
10: ALE high and ALE low pulse width = 3 SYSCLK cycles.
11: ALE high and ALE low pulse width = 4 SYSCLK cycles.
PGSEL6
R/W
R/W
Bit6
Bit6
-
Figure 17.1. EMI0CN: External Memory Interface Control
Figure 17.2. EMI0CF: External Memory Configuration
PGSEL5
PRTSEL
R/W
R/W
Bit5
Bit5
PGSEL4
EMD2
R/W
R/W
Bit4
Bit4
PGSEL3
Rev. 1.2
EMD1
R/W
R/W
Bit3
Bit3
C8051F060/1/2/3/4/5/6/7
PGSEL2
EMD0
R/W
R/W
Bit2
Bit2
PGSEL1
EALE1
R/W
R/W
Bit1
Bit1
SFR Address:
SFR Address:
SFR Page:
PGSEL0
EALE0
SFR Page:
R/W
R/W
Bit0
Bit0
0xA3
0
0xA2
0
Reset Value
Reset Value
00000000
00000011
189
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