C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 310
![DEV KIT FOR F060/F062/F063](/photos/9/23/92355/c8051f060dk_sml.jpg)
C8051F060DK
Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F060-TB.pdf
(328 pages)
Specifications of C8051F060DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F060DK
Manufacturer:
Silicon Labs
Quantity:
135
- Current page: 310 of 328
- Download datasheet (2Mb)
C8051F060/1/2/3/4/5/6/7
25.2.5. 8-Bit Pulse Width Modulator Mode
Each module can be used independently to generate pulse width modulated (PWM) outputs on its associ-
ated CEXn pin. The frequency of the output is dependent on the timebase for the PCA0 counter/timer. The
duty cycle of the PWM output signal is varied using the module's PCA0CPLn capture/compare register.
When the value in the low byte of the PCA0 counter/timer (PCA0L) is equal to the value in PCA0CPLn, the
output on the CEXn pin will be high. When the count value in PCA0L overflows, the CEXn output will be
low (see Figure 25.8). Also, when the counter/timer low byte (PCA0L) overflows from 0xFF to 0x00,
PCA0CPLn is reloaded automatically with the value stored in the counter/timer's high byte (PCA0H) with-
out software intervention. Setting the ECOMn and PWMn bits in the PCA0CPMn register enables 8-Bit
Pulse Width Modulator mode. The duty cycle for 8-Bit PWM Mode is given by Equation 25.2.
Important Note About Capture/Compare Registers: When writing a 16-bit value to the PCA0 Capture/
Compare registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn bit
to ‘0’; writing to PCA0CPHn sets ECOMn to ‘1’.
310
W
P
M
1
6
n
0
PCA0CPMn
O
M
E
C
n
C
A
P
P
n
0 0 0 0
C
A
P
N
n
M
A
T
n
O
G
T
n
W
M
P
n
C
C
E
F
n
0
PCA Timebase
Enable
PCA0CPHn
Comparator
PCA0CPLn
Figure 25.8. PCA 8-Bit PWM Mode Diagram
PCA0L
8-bit
DutyCycle
Equation 25.2. 8-Bit PWM Duty Cycle
Overflow
=
match
Rev. 1.2
-------------------------------------------------- -
256 PCA0CPHn
S
R
SET
CLR
–
Q
Q
256
CEXn
Crossbar
Port I/O
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