C8051F060DK Silicon Laboratories Inc, C8051F060DK Datasheet - Page 123
![DEV KIT FOR F060/F062/F063](/photos/9/23/92355/c8051f060dk_sml.jpg)
C8051F060DK
Manufacturer Part Number
C8051F060DK
Description
DEV KIT FOR F060/F062/F063
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F060-TB.pdf
(328 pages)
Specifications of C8051F060DK
Contents
Evaluation Board, Power Supply, USB Cables, Adapter and Documentation
Processor To Be Evaluated
C8051F06x
Interface Type
USB
Silicon Manufacturer
Silicon Labs
Core Architecture
8051
Silicon Core Number
C8051F060
Silicon Family Name
C8051F06x
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051060, C8051F062 and C8051F063
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1214
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F060DK
Manufacturer:
Silicon Labs
Quantity:
135
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13.
The MCU system controller core is the CIP-51 microcontroller. The CIP-51 is fully compatible with the
MCS-51™ instruction set; standard 803x/805x assemblers and compilers can be used to develop soft-
ware. The MCU family has a superset of all the peripherals included with a standard 8051. Included are
five 16-bit counter/timers (see description in
22
(see
includes on-chip debug hardware (see description in
analog and digital subsystems providing a complete data acquisition or control-system solution in a single
integrated circuit.
-
-
-
-
-
and
Fully Compatible with MCS-51 Instruction Set
25 MIPS Peak Throughput with 25 MHz Clock
0 to 25 MHz Clock Frequency
256 Bytes of Internal RAM
59/24 General-Purpose I/O Pins
Section
Section
CIP-51 Microcontroller
13.2.6), and 59/24 General-Purpose I/O Pins (see description in
23), 256 bytes of internal RAM, 128 byte Special Function Register (SFR) address space
Section
Rev. 1.2
24), two full-duplex UARTs (see description in
Section
-
-
-
-
-
C8051F060/1/2/3/4/5/6/7
Extended Interrupt Handler
Reset Input
Power Management Modes
On-chip Debug Logic
Program and Data Memory Security
26), and interfaces directly with the MCU’s
Section
18). The CIP-51 also
Section
123
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