DEMO9S12XEP100 Freescale Semiconductor, DEMO9S12XEP100 Datasheet - Page 1217

• Manufacturer Part Number: DEMO9S12XEP100
• Description: BOARD DEMO FOR MC9S12XEP100
• Manufacturer: Freescale Semiconductor
• Type: MCUr

Specifications of DEMO9S12XEP100

• Contents: Board, Cables, CD
• Processor To Be Evaluated: MC9S12XEP100
• Data Bus Width: 16 bit
• Interface Type: RS-232
• Silicon Manufacturer: Freescale
• Core Architecture: S12
• Core Sub-architecture: S12
• Silicon Core Number: MC9S12
• Silicon Family Name: S12XE
• Rohs Compliant: Yes
• For Use With/related Products: MC9S12XEP100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Freescale Semiconductor
Peripheral
Peripheral
S12XCPU
S12XCPU
Overhead
Overhead
MSCAN
MSCAN
XGATE
XGATE
PWM
PWM
ECT
ATD
ECT
ATD
SPI
SCI
SPI
SCI
PIT
RTI
IIC
IIC
Table A-11. Module Configurations for Maximum Run Supply Current
Table A-10. Module Configurations for Typical Run Supply Current
420 cycle loop: 384 DBNE cycles plus subroutine entry to stimulate stacking (RAM access)
XGATE fetches code from RAM, XGATE runs in an infinite loop, reading the Status and Flag
registers of CAN’s, SPI’s, SCI’s in sequence and doing some bit manipulation on the data
Configured to loop-back mode using a bit rate of 500kbit/s
Configured to master mode, continuously transmit data (0x55 or 0xAA) at 2Mbit/s
Configured into loop mode, continuously transmit data (0x55) at speed of 19200 baud
Operate in master mode and continuously transmit data (0x55 or 0xAA) at 100Kbit/s
Configured to toggle its pins at the rate of 1kHz
The peripheral shall be configured in output compare mode. Pulse accumulator and modulus
counter enabled.
The peripheral is configured to operate at its maximum specified
frequency and to continuously convert voltages on all input channels in sequence.
PIT is enabled, Micro-timer register 0 and 1 loaded with $0F and timer registers 0 to 3 are loaded
with $03/07/0F/1F.
Enabled with RTI Control Register (RTICTL) set to $59
VREG supplying 1.8V from a 5V input voltage, core clock tree active, PLL on
420 cycle loop: 384 DBNE cycles plus subroutine entry to stimulate stacking (RAM access)
XGATE fetches code from RAM, XGATE runs in an infinite loop, reading the Status and Flag
registers of CAN’s, SPI’s, SCI’s in sequence and doing some bit manipulation on the data
Configured to loop-back mode using a bit rate of 1Mbit/s
Configured to master mode, continuously transmit data (0x55 or 0xAA) at 4Mbit/s
Configured into loop mode, continuously transmit data (0x55) at speed of 57600 baud
Operate in master mode and continuously transmit data (0x55 or 0xAA) at 100Kbit/s
Configured to toggle its pins at the rate of 40kHz
The peripheral shall be configured in output compare mode. Pulse accumulator and modulus
counter enabled.
The peripheral is configured to operate at its maximum specified
frequency and to continuously convert voltages on all input channels in sequence.
VREG supplying 1.8V from a 5V input voltage, PLL on
MC9S12XE-Family Reference Manual Rev. 1.23
Configuration
Configuration
Appendix A Electrical Characteristics
V
V
DD35
DD35
=5V
=5.5V
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