CT-161-CD Fujitsu Semiconductor America Inc, CT-161-CD Datasheet - Page 34

• Manufacturer Part Number: CT-161-CD
• Description: KIT 16LX FOR MB90F387
• Manufacturer: Fujitsu Semiconductor America Inc
• Series: F²MC-16LXr
• Type: MCUr

Specifications of CT-161-CD

• Contents: Board, Cable, CD
• For Use With/related Products: MB90F387S
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 865-1103

34
MB90385 Series
4. 16-bit Input/Output Timer
(1) Functions of 16-bit free-run timer
(2) Functions of input capture
Configuration of 16-bit input/output timer
Functions of 16-bit input/output timer
The 16-bit input/output timer is a compound module composed of 16-bit free-run timer, (1 unit) and input capture
(2 units, 4 input pins). The timer, using the 16-bit free-run timer as a basis, enables measurement of clock cycle
of an input signal and its pulse width.
The 16-bit input/output timer is composed of the following modules:
• 16-bit free-run timer (1 unit)
• Input capture (2 units, 2 input pins per unit)
The 16-bit free-run timer is composed of 16-bit up counter, timer counter control status register, and prescaler.
The 16-bit up counter increments in synchronization with dividing ratio of machine clock.
• Count clock is set among four types of machine clock dividing rates.
• Generation of interrupt is allowed by counter value overflow.
• Activation of expanded intelligent I/O service (EI
• Counter value of 16-bit free-run timer is cleared to “0000
• Counter value of 16-bit free-run timer is output to input capture, which is available as base time for capture
The input capture, upon detecting an edge of a signal input to the input pin from external device, stores a counter
value of 16-bit free-run timer at the time of detection into the input capture data register. The function includes
the input capture data registers corresponding to four input pins, input capture control status register, and edge
detection circuit.
• Rising edge, falling edge, and both edges are selectable for detection.
• Generating interrupt on CPU is allowed by detecting an edge of input signal.
• Expanded intelligent I/O service (EI
• The four input capture input pins and input capture data registers allows monitoring of a maximum of four events.
count clear bit (TCCS: CLR).
operation.
2
OS) is activated by interrupt generation.
2
OS) is allowed by interrupt generation.
H
” by either resetting or software-clearing with timer