DK-DEV-3SL150N Altera, DK-DEV-3SL150N Datasheet - Page 23

• Manufacturer Part Number: DK-DEV-3SL150N
• Description: KIT DEVELOPMENT STRATIX III
• Manufacturer: Altera
• Series: Stratix® IIIr
• Type: FPGAr

Specifications of DK-DEV-3SL150N

• Contents: Development Platform, Cables and Software
• Silicon Manufacturer: Altera
• Core Architecture: FPGA
• Core Sub-architecture: Stratix
• Silicon Core Number: EP3S
• Silicon Family Name: Stratix III
• Kit Contents: Development Board, Cable And Accessories
• Rohs Compliant: Yes
• For Use With/related Products: EP3SL150F152
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 544-2568

Chapter 5: Power Measurement
Changing the Design Example
Changing the Design Example
© August 2008 Altera Corporation
1
then
Equation 5–1.
where
Voltage measurements on the DMM should increase as frequency and resource
utilization increases according to
The development kit includes source code for the Stratix III power design example so
you can use it as a starting point for your own measurements.
The design example uses 20 stamp.v modules, each with 8 outputs, for a total of
160 output pins. It assigns the pins selected as outputs to the HSMC connectors J8 and
J18.
To change the number of outputs, modify the design example and assign the pins
appropriately.
Power should track linearly with frequency and percentage resources. If you observe
superlinear power measurements, some temperature issue may be the cause.
V
SUPPLY
is 1.1 V for the FPGA core and 2.5 V for FPGA I/O.
P
=
VI
=
V
SUPPLY
Table 5–2
×
I
SENSE
and
=
Table 5–3 on page
V
---------------------------------------------
SUPPLY
R
SENSE
×
V
Stratix III Development Kit User Guide
SENSE
5–2.
5–5