EVAL-AD7725CBZ Analog Devices Inc, EVAL-AD7725CBZ Datasheet - Page 22

• Manufacturer Part Number: EVAL-AD7725CBZ
• Description: BOARD EVALUATION FOR AD7725
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD7725CBZ

• Number Of Adc's: 1
• Number Of Bits: 16
• Sampling Rate (per Second): 900k
• Data Interface: Serial, Parallel
• Inputs Per Adc: 1 Differential
• Input Range: ±VREF
• Power (typ) @ Conditions: 615mW @ 900kSPS
• Voltage Supply Source: Analog and Digital
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: AD7725
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD7725
Status Register
The status register is a 16-bit register that provides the user with
information about the status of the device. The information avail-
able to the user includes whether a configuration file was loaded
successfully, what errors if any, occurred the last instruction
written, and other information that may be useful to the user
when operating the device. To read the status register, RS is
taken high and RD/WR is taken high. When CS is taken low, the
contents of the status register will be output. The status register is
shown in Table II and the instruction set in Table III.
Bit
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Name
InstrBUSY
Data Ready
Data Request This bit is set to 1 when the device.
ID Error
CRC Error
Data Error
InstrReg[15]
InstrReg[13]
InstrReg[12]
InstrReg[11]
InstrReg[6]
InstrReg[5]
InstrReg[4]
InstrReg[1]
InstrReg[0]
CFGEND
Table II. Status Register
Function
This bit is set to 1 when an
instruction is performed.
This bit is set to 1 when data is
ready to be read from the device
(a read data cycle is required).
requires data to be written to it (a write
data cycle is required).
This bit is set to 1 if the programming
data has an incorrect ID value.
This bit is set to 1 if corrupt
data is loaded into the device.
This bit is set to 1 if an overflow occurs
to indicate that the conversion result is
invalid.
Instruction Register Bit 15
Instruction Register Bit 13
Instruction Register Bit 12
Instruction Register Bit 11
Instruction Register Bit 6
Instruction Register Bit 5
Instruction Register Bit 4
Instruction Register Bit 1
Instruction Register Bit 0
Configuration End Flag. This is set to 1
when the device has been configured
correctly and is ready to start converting.
–22–
Instruction
RdID
RdCONV
WrConfig
WrConfigEM
ABORT
BFR
Configuring the Device
Following power-up, the AD7725 is configured by loading a user-
defined filter from an external source via the parallel interface.
Three instructions are provided for configuring the AD7725 (see
Table III).
•
•
For evaluation purposes, the user can load the default filter
stored in internal ROM into the postprocessor. In this case the
following instruction should be issued:
•
WrConfig (Write Configuration)
When this instruction is issued, the device generates an
interrupt every time a new word of the configuration data is
required. The interrupt is cleared on the falling edge of CS
during the data write cycle. This continues until the com-
plete file is written. Immediately after the last word of the
configuration data is written, a final interrupt is asserted to
indicate “Instruction Done.”
However, if an error occurred during the configuration
process, for example, if the configuration data is corrupt or
in the wrong format, an interrupt will be asserted.
It is advised that when using this instruction, the status regis-
ter be read after each interrupt to ensure no errors occurred
and that the correct response is made. If configuration data is
corrupt, it will not be internally written to the postprocessor.
WrConfigEM (Write Configuration with Error Mask)
When this instruction is issued, no interrupts to signal errors
will ever be asserted during the download of the configura-
tion file. This saves reading the status register in response
to every interrupt as with the previous instruction. The
configuration process will always run through the 504
(42 writes
tion file and once this is complete, the “Instruction Done”
interrupt is issued. In this case, the status register should be
checked at the end of the configuration to verify whether
any errors occurred. If configuration data is corrupt, it will
not be internally written to the postprocessor.
BFR (Boot from ROM)
This instruction informs the device to load the configuration
data for the default filter stored in internal ROM.
Table III. Instruction Set for Parallel Mode
Hex Code
0x8802
0x8D21
0x1800
0x1A00
0x0000
0x2000
12 blocks) data write cycles in the configura-
Description
Read Device ID
Read Converter Data. When
this instruction is issued to the
AD7725, the device continues to
output conversion data until the
ABORT instruction is issued.
Write Configuration Data
Write Configuration Data,
Mask Errors
Abort. This instruction is a
soft reset, that is, it breaks the
conversion process and leaves
the device in a clean state,
still configured, ready for the
next instruction.
Boot from Internal ROM
REV. A