EVAL-AD7944EBZ Analog Devices Inc, EVAL-AD7944EBZ Datasheet - Page 17

BOARD EVAL FOR AD7944

EVAL-AD7944EBZ

Manufacturer Part Number
EVAL-AD7944EBZ
Description
BOARD EVAL FOR AD7944
Manufacturer
Analog Devices Inc
Series
PulSAR®r
Datasheet

Specifications of EVAL-AD7944EBZ

Number Of Adc's
1
Number Of Bits
14
Sampling Rate (per Second)
2.5M
Data Interface
SPI™, QSPI™, MICROWIRE™, and DSP
Inputs Per Adc
1 Differential
Input Range
0 ~ 5 V
Voltage Supply Source
Analog and Digital
Operating Temperature
-40°C ~ 85°C
Utilized Ic / Part
AD7944
Silicon Manufacturer
Analog Devices
Application Sub Type
ADC
Kit Application Type
Data Converter
Silicon Core Number
AD7944
Kit Contents
Board And Literature
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
DIGITAL INTERFACE
Although the AD7944 has a reduced number of pins, it offers
flexibility in its serial interface modes.
In CS mode, the AD7944 is compatible with SPI, MICROWIRE™,
QSPI™, and digital hosts. In CS mode, the AD7944 can use either
a 3-wire or a 4-wire interface. A 3-wire interface that uses the
CNV, SCK, and SDO signals minimizes wiring connections,
which is useful, for example, in isolated applications. A 4-wire
interface that uses the SDI, CNV, SCK, and SDO signals allows
CNV, which initiates conversions, to be independent of the
readback timing (SDI). This is useful in low jitter sampling or
simultaneous sampling applications.
In chain mode, the AD7944 provides a daisy-chain feature that
uses the SDI input for cascading multiple ADCs on a single data
line similar to a shift register. Chain mode is available only in
normal conversion mode (TURBO low).
The mode in which the part operates depends on the SDI level
when the CNV rising edge occurs. CS mode is selected if SDI
is high, and chain mode is selected if SDI is low. The SDI hold
time is such that when SDI and CNV are connected together,
chain mode is always selected.
In normal mode operation, the AD7944 offers the option of
forcing a start bit in front of the data bits. This start bit can be
used as a busy signal indicator to interrupt the digital host and
trigger the data reading. Otherwise, without a busy indicator,
the user must time out the maximum conversion time prior to
readback.
The busy indicator feature is enabled in CS mode if CNV or
SDI is low when the ADC conversion ends (see Figure 29 and
Figure 33). TURBO must be kept low for both digital interfaces.
Table 9 lists the availability of each serial interface mode, with
and without the busy indicator, for the two conversion modes.
Rev. A | Page 17 of 28
Table 9. Serial Interface Modes ( CS
Each Conversion Mode (Turbo and Normal)
Serial Interface Mode
CS Mode, 3-Wire
CS Mode, 4-Wire
Chain Mode
When CNV is low, readback can occur during conversion or
acquisition, or it can be split across acquisition and conversion,
as described in the following sections.
A discontinuous SCK is recommended because the part is selected
with CNV low, and SCK activity begins to clock out data.
Note that in the following sections, the timing diagrams indicate
digital activity (SCK, CNV, SDI, and SDO) during the conversion.
However, due to the possibility of performance degradation,
digital activity should occur only prior to the safe data reading
time, t
circuitry that can correct for an incorrect bit decision during
this time. From t
conversion results may be corrupted.
Similarly, t
the rising edge of CNV, must remain free of digital activity.
The user should configure the AD7944 and initiate the busy
indicator (if desired in normal mode) prior to t
It is also possible to corrupt the sample by having SCK near the
sampling instant. Therefore, it is recommended that the digital
pins be kept quiet for approximately 20 ns before and 10 ns after
the rising edge of CNV, using a discontinuous SCK whenever
possible to avoid any potential performance degradation.
Without Busy Indicator
With Busy Indicator
Without Busy Indicator
With Busy Indicator
Without Busy Indicator
With Busy Indicator
DATA
, because the AD7944 provides error correction
QUIET
, the time from the last falling edge of SCK to
DATA
to t
CONV
Turbo Mode
Yes
No
Yes
No
No
No
, there is no error correction, and
Conversion Mode
and Chain Mode) for
Normal Mode
Yes
Yes
Yes
Yes
Yes
Yes
DATA
.
AD7944

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