ADC1415S125/DB,598 NXP Semiconductors, ADC1415S125/DB,598 Datasheet - Page 29

• Manufacturer Part Number: ADC1415S125/DB,598
• Description: BOARD DEMO FOR ADC1415S125
• Manufacturer: NXP Semiconductors
• Type: A/Dr

Specifications of ADC1415S125/DB,598

• Number Of Adc's: 1
• Number Of Bits: 14
• Sampling Rate (per Second): 125M
• Data Interface: Serial, SPI™
• Inputs Per Adc: 1 Differential
• Input Range: 1 ~ 2 Vpp
• Power (typ) @ Conditions: 840mW @ 125Msps
• Voltage Supply Source: Single Supply
• Operating Temperature: -40°C ~ 85°C
• Utilized Ic / Part: ADC1415S125
• Product: Data Conversion Development Tools
• Conversion Rate: 125 MSPS
• Resolution: 14 bit
• Interface Type: SMA
• For Use With/related Products: ADC1415S125
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 568-5094

NXP Semiconductors
ADC1415S_SER
Product data sheet
Fig 28. SPI mode timing
SCLK
SDIO
CS
R/W W1
11.6.2 Default modes at start-up
W0 A12 A11 A10
Table 17.
Bits A12 to A0 indicate the address of the register being accessed. In the case of a
multiple byte transfer, this address is the first register to be accessed. An address counter
is increased to access subsequent addresses.
The steps involved in a data transfer are as follows:
During circuit initialization it does not matter which output data standard has been
selected. At power-up, the device enters Pin control mode.
A falling edge on CS triggers a transition to SPI control mode. When the ADC1415S
enters SPI control mode, the output data standard (CMOS/LVDS DDR) is determined by
the level on pin SDIO (see
can be changed via bit LVDS/CMOS in
When the ADC1415S enters SPI control mode, the output data format (two’s complement
or offset binary) is determined by the level on pin SCLK (gray code can only be selected
via the SPI). Once in SPI control mode, the output data format can be changed via bit
DATA_FORMAT[1:0] in
W1
0
0
1
1
1. A falling edge on CS in combination with a rising edge on SCLK determine the start of
2. The first phase is the transfer of the 2-byte instruction.
3. The second phase is the transfer of the data which can vary in length but is always a
4. A rising edge on CS indicates the end of data transmission.
communications.
multiple of 8 bits. The MSB is always sent first (for instruction and data bytes).
A9
Instruction bytes
A8
Number of data bytes to be transferred after the instruction bytes
W0
0
1
0
1
A7
A6
All information provided in this document is subject to legal disclaimers.
Single 14-bit ADC; input buffer; CMOS or LVDS DDR digital outputs
A5
1 byte
2 bytes
3 bytes
4 bytes or more
Number of bytes transmitted
A4
Rev. 4 — 17 December 2010
Table
A3
Figure
A2
23.
A1
A0
29). Once in SPI control mode, the output data standard
D7
D6
Table
D5
Register N (data)
D4
23.
D3
D2
ADC1415S series
D1
D0
D7
D6
D5
Register N + 1 (data)
D4
© NXP B.V. 2010. All rights reserved.
D3
D2
D1
005aaa062
D0
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